Merge pull request #59 from siliconcompiler/auxlibs

Auxlibs

lambdapdk/asap7/libs/asap7sc7p5t.py

@@ -120,11 +120,15 @@ def _setup_lib(chip, libname, suffix):
     lib.set('option', 'file', 'openroad_global_connect',
             libdir + '/apr/openroad/global_connect.tcl')
 
-    lambda_lib = siliconcompiler.Library(chip, f'lambdalib_{libname}', package='lambdapdk')
-    register_data_source(lambda_lib)
-    lambda_lib.add('option', 'ydir', libdir + '/lambda')
+    libs = [lib]
+    for libtype in ('stdlib', 'auxlib'):
+        lambda_lib = siliconcompiler.Library(chip, f'lambdalib_{libtype}_{libname}',
+                                             package='lambdapdk')
+        register_data_source(lambda_lib)
+        lambda_lib.add('option', 'ydir', libdir + f'/lambda/{libtype}')
+        libs.append(lambda_lib)
 
-    return [lib, lambda_lib]
+    return libs
 
 
 def setup(chip):

lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_clkicgand.v

@@ -0,0 +1,24 @@
+//#############################################################################
+//# Function: Integrated "And" Clock Gating Cell (And)                        #
+//# Copyright: Lambda Project Authors. All rights Reserved.                   #
+//# License:  MIT (see LICENSE file in Lambda repository)                     #
+//#############################################################################
+
+module la_clkicgand #(
+    parameter PROP = "DEFAULT"
+) (
+    input  clk,  // clock input
+    input  te,   // test enable
+    input  en,   // enable (from positive edge FF)
+    output eclk  // enabled clock output
+);
+
+    // reg en_stable;
+
+    // always @(clk or en or te) if (~clk) en_stable <= en | te;
+
+    // assign eclk = clk & en_stable;
+
+ICGx1_ASAP7_75t_L u0(.CLK(clk), .ENA(en), .SE(te), .GCK(eclk));
+
+endmodule

lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_clkicgor.v

@@ -0,0 +1,30 @@
+//#############################################################################
+//# Function: Integrated "Or" Clock Gating Cell                               #
+//# Copyright: Lambda Project Authors. All rights Reserved.                   #
+//# License:  MIT (see LICENSE file in Lambda repository)                     #
+//#############################################################################
+
+module la_clkicgor #(
+    parameter PROP = "DEFAULT"
+) (
+    input  clk,  // clock input
+    input  te,   // test enable
+    input  en,   // enable
+    output eclk  // enabled clock output
+);
+
+    // reg en_stable;
+
+    // always @(clk or en or te) if (clk) en_stable <= en | te;
+
+    // assign eclk = clk | ~en_stable;
+
+wire eclk_int;
+wire en_bar;
+
+ICGx1_ASAP7_75t_L u0(.CLK(clk), .ENA(en), .SE(te), .GCK(eclk_int));
+
+INVx1_ASAP7_75t_L u1(.A(en), .Y(en_bar));
+OR2x2_ASAP7_75t_L u2(.A(en_bar), .B(eclk_int), .Y(eclk));
+
+endmodule

lambdapdk/asap7/libs/asap7sc7p5t_slvt/lambda/la_decap.v → lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_decap.v

@@ -11,4 +11,6 @@ module la_decap #(
     output vdd
 );
 
+DECAPx10_ASAP7_75t_L u0(.VSS(vss), .VDD(vdd));
+
 endmodule

lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/la_drsync.v → lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_drsync.v

@@ -24,7 +24,7 @@
 // 
 // endmodule
 
-/* Generated by Yosys 0.40 (git sha1 a1bb0255d, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */
+/* Generated by Yosys 0.41 (git sha1 c1ad37779, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */
 
 module la_drsync(clk, in, nreset, out);
   wire _0_;
@@ -39,11 +39,11 @@ module la_drsync(clk, in, nreset, out);
   output out;
   wire out;
   wire \shiftreg[0] ;
-  INVx1_ASAP7_75t_L _3_ (
+  INVx2_ASAP7_75t_L _3_ (
     .A(_0_),
     .Y(out)
   );
-  INVx1_ASAP7_75t_L _4_ (
+  INVx2_ASAP7_75t_L _4_ (
     .A(_1_),
     .Y(\shiftreg[0] )
   );

lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_dsync.v

@@ -0,0 +1,51 @@
+//#############################################################################
+//# Function: Synchronizer                                                    #
+//# Copyright: Lambda Project Authors. All rights Reserved.                   #
+//# License:  MIT (see LICENSE file in Lambda repository)                     #
+//#############################################################################
+module la_dsync #(parameter PROP = "DEFAULT",
+                  parameter STAGES = 2,       // synchronizer depth
+                  parameter RND = 1)          // randomize simulation delay
+   (
+    input  clk, // clock
+    input  in, // input data
+    output out  // synchronized data
+    );
+
+//    reg [STAGES:0] shiftreg;
+//    always @(posedge clk)
+//      shiftreg[STAGES:0] <= {shiftreg[STAGES-1:0], in};
+
+// `ifdef SIM
+//    integer        sync_delay;
+//    always @(posedge clk)
+//      sync_delay <= {$random} % 2;
+//    assign out = (|sync_delay & (|RND)) ? shiftreg[STAGES] : shiftreg[STAGES-1];
+// `else
+//    assign out = shiftreg[STAGES-1];
+// `endif
+
+   genvar i;
+   generate
+      for (i = 0; i < STAGES; i = i + 1) begin: DELAY
+         wire reg_in;
+         wire reg_out;
+         if (i == 0) begin: SEL_IN
+            assign reg_in = in;
+         end else begin: SEL_PREV
+            assign reg_in = reg_out[i - 1];
+         end
+
+         wire reg_out_int;
+         DFFHQNx1_ASAP7_75t_L u0 (
+            .CK(clk),
+            .D(reg_in),
+            .QN(reg_out_int)
+         );
+         INVx1_ASAP7_75t_L u1(.A(reg_out_int), .Y(reg_out));
+      end
+   endgenerate
+
+   assign out = DELAY[STAGES - 1].reg_out;
+
+endmodule

lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/la_iddr.v → lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_iddr.v

@@ -25,7 +25,7 @@
 // 
 // endmodule
 
-/* Generated by Yosys 0.40 (git sha1 a1bb0255d, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */
+/* Generated by Yosys 0.41 (git sha1 c1ad37779, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */
 
 module la_iddr(clk, in, outrise, outfall);
   wire _0_;
@@ -39,11 +39,11 @@ module la_iddr(clk, in, outrise, outfall);
   wire outfall;
   output outrise;
   wire outrise;
-  INVx1_ASAP7_75t_L _2_ (
+  INVx2_ASAP7_75t_L _2_ (
     .A(_0_),
     .Y(outfall)
   );
-  INVx1_ASAP7_75t_L _3_ (
+  INVx2_ASAP7_75t_L _3_ (
     .A(_1_),
     .Y(inrise)
   );

lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/la_isohi.v → lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_isohi.v

@@ -16,7 +16,7 @@
 // 
 // endmodule
 
-/* Generated by Yosys 0.40 (git sha1 a1bb0255d, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */
+/* Generated by Yosys 0.41 (git sha1 c1ad37779, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */
 
 module la_isohi(iso, in, out);
   input in;

lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/la_isolo.v → lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_isolo.v

@@ -16,7 +16,7 @@
 // 
 // endmodule
 
-/* Generated by Yosys 0.40 (git sha1 a1bb0255d, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */
+/* Generated by Yosys 0.41 (git sha1 c1ad37779, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */
 
 module la_isolo(iso, in, out);
   wire _0_;
@@ -30,7 +30,7 @@ module la_isolo(iso, in, out);
     .A(iso),
     .Y(_0_)
   );
-  AND2x2_ASAP7_75t_L _2_ (
+  AND2x4_ASAP7_75t_L _2_ (
     .A(in),
     .B(_0_),
     .Y(out)

lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/la_oddr.v → lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_oddr.v

@@ -22,7 +22,7 @@
 // 
 // endmodule
 
-/* Generated by Yosys 0.40 (git sha1 a1bb0255d, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */
+/* Generated by Yosys 0.41 (git sha1 c1ad37779, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */
 
 module la_oddr(clk, in0, in1, out);
   wire _0_;
@@ -40,7 +40,7 @@ module la_oddr(clk, in0, in1, out);
     .A(clk),
     .Y(_0_)
   );
-  AND2x4_ASAP7_75t_L _3_ (
+  AND2x2_ASAP7_75t_L _3_ (
     .A(in1_sh),
     .B(clk),
     .Y(_1_)

lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu9t5v0/lambda/la_antenna.v → lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_pwrbuf.v

@@ -1,12 +1,19 @@
 //#############################################################################
-//# Function: Antenna Diode                                                   #
+//# Function: Non-inverting buffer with supplies                              #
 //# Copyright: Lambda Project Authors. All rights Reserved.                   #
 //# License:  MIT (see LICENSE file in Lambda repository)                     #
 //#############################################################################
 
-module la_antenna #(parameter PROP = "DEFAULT")   (
+module la_pwrbuf #(
+                   parameter PROP = "DEFAULT"
+                   )
+   (
+    input  vdd,
     input  vss,
+    input  a,
     output z
     );
 
+BUFx2_ASAP7_75t_L u0(.A(a), .Y(z), .VSS(vss), .VDD(vdd));
+
 endmodule

lambdapdk/asap7/libs/asap7sc7p5t_lvt/lambda/auxlib/la_rsync.v

@@ -0,0 +1,64 @@
+//#############################################################################
+//# Function:  Reset synchronizer (async assert, sync deassert)               #
+//# Copyright: Lambda Project Authors. All rights Reserved.                   #
+//# License:   MIT (see LICENSE file in Lambda repository)                    #
+//#############################################################################
+module la_rsync #(parameter PROP = "DEFAULT",
+                  parameter STAGES = 2,       // synchronizer depth
+                  parameter RND = 1)          // randomize sync
+
+   (
+    input  clk,     // clock
+    input  nrst_in, // async reset input
+    output nrst_out // async assert, sync deassert reset
+    );
+
+//    reg     [STAGES:0] sync_pipe;
+//    integer            sync_delay;
+
+
+//    always @(posedge clk or negedge nrst_in)
+//      if (!nrst_in)
+//        sync_pipe[STAGES:0] <= 'b0;
+//      else
+//        sync_pipe[STAGES:0] <= {sync_pipe[STAGES-1:0], 1'b1};
+
+// `ifdef SIM
+//    always @(posedge clk)
+//      sync_delay <= {$random} % 2;
+
+//    assign nrst_out = (|sync_delay & (|RND)) ? sync_pipe[STAGES] : sync_pipe[STAGES-1];
+// `else
+//    assign nrst_out = sync_pipe[STAGES-1];
+// `endif
+
+   genvar i;
+   generate
+      for (i = 0; i < STAGES; i = i + 1) begin: DELAY
+         wire reg_in;
+         wire reg_out;
+         if (i == 0) begin: SEL_IN
+            LOGIC1_X1 u1 (
+              .Z(reg_in)
+            );
+         end else begin: SEL_PREV
+            assign reg_in = reg_out[i - 1];
+         end
+
+         wire reg_out_int;
+         wire setn;
+         TIEHIx1_ASAP7_75t_L u1(.H(setn));
+         DFFASRHQNx1_ASAP7_75t_L u0 (
+            .CK(clk),
+            .RESETN(nrest_in),
+            .SETN(setn),
+            .D(reg_in),
+            .QN(reg_out_int)
+         );
+         INVx1_ASAP7_75t_L u2(.A(reg_out_int), .Y(reg_out));
+      end
+   endgenerate
+
+   assign nrst_out = DELAY[STAGES - 1].reg_out;
+
+endmodule