Merge pull request #54 from siliconcompiler/fix-synlinks-windows

fix symbolic links

lambdapdk/asap7/libs/asap7sc7p5t_lvt/apr/openroad/global_connect.tcl

@@ -0,0 +1,5 @@
+####################################
+# global connections
+####################################
+add_global_connection -net {VDD} -pin_pattern {VDD} -power
+add_global_connection -net {VSS} -pin_pattern {VSS} -ground

lambdapdk/asap7/libs/asap7sc7p5t_lvt/apr/openroad/pdngen.tcl

@@ -0,0 +1,15 @@
+####################################
+# voltage domains
+####################################
+set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
+####################################
+# standard cell grid
+####################################
+define_pdn_grid -name {top} -voltage_domains {CORE}
+add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
+add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins
+add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {5.904} -offset {0.300}
+add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {6.0} -offset {0.513}
+add_pdn_connect -grid {top} -layers {M1 M2}
+add_pdn_connect -grid {top} -layers {M2 M5}
+add_pdn_connect -grid {top} -layers {M5 M6}

lambdapdk/asap7/libs/asap7sc7p5t_lvt/apr/openroad/tracks.tcl

@@ -0,0 +1,18 @@
+make_tracks Pad -x_offset 0.116 -x_pitch 0.08 -y_offset 0.116 -y_pitch 0.08
+make_tracks M9 -x_offset 0.116 -x_pitch 0.08 -y_offset 0.116 -y_pitch 0.08
+make_tracks M8 -x_offset 0.116 -x_pitch 0.08 -y_offset 0.116 -y_pitch 0.08
+make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064
+make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064
+make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048
+make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048
+make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036
+
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270
+
+make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036

lambdapdk/asap7/libs/asap7sc7p5t_rvt/apr/openroad/global_connect.tcl

@@ -0,0 +1,5 @@
+####################################
+# global connections
+####################################
+add_global_connection -net {VDD} -pin_pattern {VDD} -power
+add_global_connection -net {VSS} -pin_pattern {VSS} -ground

lambdapdk/asap7/libs/asap7sc7p5t_rvt/apr/openroad/pdngen.tcl

@@ -0,0 +1,15 @@
+####################################
+# voltage domains
+####################################
+set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
+####################################
+# standard cell grid
+####################################
+define_pdn_grid -name {top} -voltage_domains {CORE}
+add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
+add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins
+add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {5.904} -offset {0.300}
+add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {6.0} -offset {0.513}
+add_pdn_connect -grid {top} -layers {M1 M2}
+add_pdn_connect -grid {top} -layers {M2 M5}
+add_pdn_connect -grid {top} -layers {M5 M6}

lambdapdk/asap7/libs/asap7sc7p5t_rvt/apr/openroad/tracks.tcl

@@ -0,0 +1,18 @@
+make_tracks Pad -x_offset 0.116 -x_pitch 0.08 -y_offset 0.116 -y_pitch 0.08
+make_tracks M9 -x_offset 0.116 -x_pitch 0.08 -y_offset 0.116 -y_pitch 0.08
+make_tracks M8 -x_offset 0.116 -x_pitch 0.08 -y_offset 0.116 -y_pitch 0.08
+make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064
+make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064
+make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048
+make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048
+make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036
+
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270
+
+make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036

lambdapdk/asap7/libs/asap7sc7p5t_slvt/apr/openroad/global_connect.tcl

@@ -0,0 +1,5 @@
+####################################
+# global connections
+####################################
+add_global_connection -net {VDD} -pin_pattern {VDD} -power
+add_global_connection -net {VSS} -pin_pattern {VSS} -ground

lambdapdk/asap7/libs/asap7sc7p5t_slvt/apr/openroad/pdngen.tcl

@@ -0,0 +1,15 @@
+####################################
+# voltage domains
+####################################
+set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
+####################################
+# standard cell grid
+####################################
+define_pdn_grid -name {top} -voltage_domains {CORE}
+add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
+add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins
+add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {5.904} -offset {0.300}
+add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {6.0} -offset {0.513}
+add_pdn_connect -grid {top} -layers {M1 M2}
+add_pdn_connect -grid {top} -layers {M2 M5}
+add_pdn_connect -grid {top} -layers {M5 M6}

lambdapdk/asap7/libs/asap7sc7p5t_slvt/apr/openroad/tracks.tcl

@@ -0,0 +1,18 @@
+make_tracks Pad -x_offset 0.116 -x_pitch 0.08 -y_offset 0.116 -y_pitch 0.08
+make_tracks M9 -x_offset 0.116 -x_pitch 0.08 -y_offset 0.116 -y_pitch 0.08
+make_tracks M8 -x_offset 0.116 -x_pitch 0.08 -y_offset 0.116 -y_pitch 0.08
+make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064
+make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064
+make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048
+make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048
+make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036
+
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270
+make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270
+
+make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036

lambdapdk/sky130/libs/sky130hdll/apr/openroad/global_connect.tcl

@@ -0,0 +1,9 @@
+####################################
+# global connections
+####################################
+add_global_connection -net {VDD} -pin_pattern {VDD} -power
+add_global_connection -net {VDD} -pin_pattern {VPWR}
+add_global_connection -net {VDD} -pin_pattern {VPB}
+add_global_connection -net {VSS} -pin_pattern {VSS} -ground
+add_global_connection -net {VSS} -pin_pattern {VGND}
+add_global_connection -net {VSS} -pin_pattern {VNB}

lambdapdk/sky130/libs/sky130hdll/apr/openroad/pdngen.tcl

@@ -0,0 +1,23 @@
+####################################
+# voltage domains
+####################################
+set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
+####################################
+# standard cell grid
+####################################
+define_pdn_grid -name {grid} -voltage_domains {CORE}
+add_pdn_stripe -grid {grid} -layer {met1} -width {0.48} -pitch {5.44} -offset {0} -followpins
+set met4_pitch [expr {([lindex [ord::get_core_area] 2] - [lindex [ord::get_core_area] 0]) / 2}]
+if {$met4_pitch > 27.140} {
+    set met4_pitch 27.140
+}
+set met5_pitch [expr {([lindex [ord::get_core_area] 3] - [lindex [ord::get_core_area] 1]) / 2}]
+if {$met5_pitch > 27.200} {
+    set met5_pitch 27.200
+}
+add_pdn_stripe -grid {grid} -layer {met4} -width {1.600} -pitch $met4_pitch \
+    -offset [expr {$met4_pitch / 4}]
+add_pdn_stripe -grid {grid} -layer {met5} -width {1.600} -pitch $met5_pitch \
+    -offset [expr {$met5_pitch / 4}]
+add_pdn_connect -grid {grid} -layers {met1 met4}
+add_pdn_connect -grid {grid} -layers {met4 met5}