fix various typos

README.md

@@ -1,6 +1,6 @@
 # Lambdalib Introduction
 
-Lambdalib is a modular hardware abstraction library decouples design from the uderlying manufacturing target. Lambdalib defines a set of generic functions that get resolved during the target technology mapping stage.
+Lambdalib is a modular hardware abstraction library decouples design from the underlying manufacturing target. Lambdalib defines a set of generic functions that get resolved during the target technology mapping stage.
 
 Lambdalib includes the following hardware categories:
 

lambdalib/auxlib/rtl/la_oddr.v

@@ -17,7 +17,7 @@ module la_oddr #(
     reg in1_sh;
     always @(clk or in1) if (~clk) in1_sh <= in1;
 
-    //Using clock as data selctor
+    //Using clock as data selector
     assign out = clk ? in1_sh : in0;
 
 endmodule

lambdalib/fpgalib/rtl/la_clb4p0.v

@@ -25,7 +25,7 @@
  *
  * 1. N=2, I=4
  * 2. test1: CLB configured as separate and4, or4 gates
- * 3. test2" LB confiugred as combined and7 (in[7]=ignored)
+ * 3. test2" LB configured as combined and7 (in[7]=ignored)
  *
  ******************************************************************************/
 

lambdalib/iolib/README.md

@@ -6,7 +6,7 @@
 | ---------------------------------|---------|-----------------------------|
 [[la_iobidir](./rtl/la_iobidir.v)  | Digital | Bidirectional
 [la_ioinput](./rtl/la_ioinput.v)   | Digital | Input
-[la_ioxtal](./rtl/la_ioxtal.v)     | Digital | Xtal tranceiver
+[la_ioxtal](./rtl/la_ioxtal.v)     | Digital | Xtal transceiver
 [la_iorxdiff](./rtl/la_iorxdiff.v) | Digital | Differential input
 [la_iotxdiff](./rtl/la_iotxdiff.v) | Digital | Differential output
 [la_ioanalog](./rtl/la_ioanalog.v) | Analog  | Pass through ESD protection
@@ -24,7 +24,7 @@
 ## PARAMETERS
 
 ### CFGW
-The `CFGW` parameter defines the width of the configuration bus of the io cell. IO cells generally include a set of configuration inputs for things like drive strength and operating modes. Setting `CFGW` to a large value (eg. 16/32) should have zero impact on the design as the extra bus bits get optimized away during implementation. The connection between the generic `CFG` bus and the technology specific IO cell is done within the techology specific cell wrapper library.
+The `CFGW` parameter defines the width of the configuration bus of the io cell. IO cells generally include a set of configuration inputs for things like drive strength and operating modes. Setting `CFGW` to a large value (eg. 16/32) should have zero impact on the design as the extra bus bits get optimized away during implementation. The connection between the generic `CFG` bus and the technology specific IO cell is done within the technology specific cell wrapper library.
 
 For la_bidir, the first 8 bits of the configuration bus are reserved for the functionality shown in the table below.
 

lambdalib/padring/README.md

@@ -7,7 +7,7 @@ The lamdbdalib `padring` library is an automated "pure verilog" padring generato
 ## PARAMETERS
 
 ### {NO,EA,WE,SO}NCELLS
-Specifies the total number of placed cells within one side of the padring, includig supply and clamp cells.
+Specifies the total number of placed cells within one side of the padring, including supply and clamp cells.
 
 ### {NO,EA,WE,SO}NPINS
 Specifies the total number of logical device pins (pads) connected to one side of the padring, not including supply pins. The `CELLMAP` parameter specifies which one of the pins should be connected to a cell.

lambdalib/padring/__init__.py

@@ -8,7 +8,7 @@
 ########################
 def setup(chip):
     '''
-    Lambdalib pandring
+    Lambdalib padring
     '''
 
     lib = Library(chip, 'lambdalib_padring', package='lambdalib', auto_enable=True)

lambdalib/ramlib/rtl/la_asyncfifo.v

@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_dpram" would generally include
- * one ore more hardcoded instantiations of RAM modules with a generate
+ * one or more hardcoded instantiations of RAM modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *

lambdalib/ramlib/rtl/la_dpram.v

@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_dpram" would generally include
- * one ore more hardcoded instantiations of RAM modules with a generate
+ * one or more hardcoded instantiations of RAM modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *

lambdalib/ramlib/rtl/la_spram.v

@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_spram" would generally include
- * one ore more hardcoded instantiations of RAM modules with a generate
+ * one or more hardcoded instantiations of RAM modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *

lambdalib/ramlib/rtl/la_spregfile.v

@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_spregfile" would generally
- * include one ore more hardcoded instantiations of RF modules with a generate
+ * include one or more hardcoded instantiations of RF modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *

lambdalib/utils/templates/la_spmemory.v

@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_sp{{ type }}" would generally include
- * one ore more hardcoded instantiations of {{ type }} modules with a generate
+ * one or more hardcoded instantiations of {{ type }} modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *