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Add support for riscv64 architecture#229

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eshattow:riscv64
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Add support for riscv64 architecture#229
eshattow wants to merge 1 commit into
sigstore:mainfrom
eshattow:riscv64

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@eshattow eshattow commented Apr 7, 2026

Upstream cosign offers riscv64 binaries for download, and so let's add support for the riscv64 architecture in cosign-installer.

Summary

RISE RISC-V runners are generally available now, similar to self-hosted runners. So while GitHub itself does not (yet) have RISC-V Tier-1 runners it is now likely that cosign-installer GitHub Action would be called "in the wild" for RISC-V architecture.

Release Note

RISC-V support only for Linux; Not applicable to MacOS and Windows

Documentation

Unsure if this needs to be documented further.

Resolves: #228

@eshattow eshattow mentioned this pull request Apr 13, 2026
@eshattow eshattow marked this pull request as draft April 16, 2026 12:37
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Depend on #232 for bootstrap_* env vars and convert PR to draft, pending completion of #232.

@eshattow eshattow marked this pull request as ready for review April 22, 2026 07:22
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I'm going to generalize this in future as in #233 but meanwhile please consider applying this pull request after applying #232

@eshattow eshattow force-pushed the riscv64 branch 4 times, most recently from c1bcf84 to c6ea346 Compare April 22, 2026 07:50
Upstream cosign offers riscv64 binaries for download, and so let's add
support for the riscv64 architecture in cosign-installer.

Resolves sigstore#228

Signed-off-by: E Shattow <eshattow@users.noreply.github.com>
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eshattow commented May 7, 2026

rebased on main now that #232 is completed

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eshattow commented May 7, 2026

FYI if we do changes-requested to add the other remaining platforms I would accept that and adjust the commit messages appropriately, it would still resolve my concern #228 ; else this is fine until generalizing this out in next-after release of cosign-installer and apologies to PowerPC and S/390 users of sigstore/cosign-installer, speak up if you need this...

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Support RISC-V

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