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arm: tegra: grouper: memory: update DVFS table (ver: 0704_15R7)
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According to Tegra3 Errata v6 torvalds#26 (Rare memory controller deadlock
condition)

Bug 1013627 Rare memory controller deadlock condition (regarding to EACK)
Bug 955082

Change-Id: I696a275b3921e485da195bf4d5f772c2d0050beb
Signed-off-by: Haley Teng <[email protected]>
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Haley Teng authored and singhome_lee committed Jul 10, 2012
1 parent 3ef6a08 commit 3c7c577
Showing 1 changed file with 26 additions and 26 deletions.
52 changes: 26 additions & 26 deletions arch/arm/mach-tegra/board-grouper-memory.c
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@
#include "fuse.h"


static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = {
static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0704_15R7[] = {
{
0x32, /* Rev 3.2 */
25500, /* SDRAM frequency */
Expand Down Expand Up @@ -117,7 +117,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = {
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
0x00020001, /* MC_EMEM_ARB_CFG */
0x00030003, /* MC_EMEM_ARB_CFG */
0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -237,7 +237,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = {
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
0x00010001, /* MC_EMEM_ARB_CFG */
0x00010003, /* MC_EMEM_ARB_CFG */
0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -357,7 +357,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = {
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
0x00000001, /* MC_EMEM_ARB_CFG */
0x00000003, /* MC_EMEM_ARB_CFG */
0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -477,7 +477,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = {
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
0x00000003, /* MC_EMEM_ARB_CFG */
0x00000006, /* MC_EMEM_ARB_CFG */
0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -597,7 +597,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = {
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */
0x00000005, /* MC_EMEM_ARB_CFG */
0x0000000a, /* MC_EMEM_ARB_CFG */
0xc000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000002, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -717,7 +717,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = {
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
0x0000000a, /* MC_EMEM_ARB_CFG */
0x00000014, /* MC_EMEM_ARB_CFG */
0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
0x00000004, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -748,7 +748,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = {
},
};

static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={
static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0704_15R7[] = {
{
0x32, /* Rev 3.2 */
25500, /* SDRAM frequency */
Expand Down Expand Up @@ -840,7 +840,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
0x00020001, /* MC_EMEM_ARB_CFG */
0x00030003, /* MC_EMEM_ARB_CFG */
0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -960,7 +960,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
0x00010001, /* MC_EMEM_ARB_CFG */
0x00010003, /* MC_EMEM_ARB_CFG */
0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -1080,7 +1080,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
0x00000001, /* MC_EMEM_ARB_CFG */
0x00000003, /* MC_EMEM_ARB_CFG */
0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -1200,7 +1200,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
0x00000003, /* MC_EMEM_ARB_CFG */
0x00000006, /* MC_EMEM_ARB_CFG */
0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -1320,7 +1320,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */
0x00000005, /* MC_EMEM_ARB_CFG */
0x0000000a, /* MC_EMEM_ARB_CFG */
0xc000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000002, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -1440,7 +1440,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
0x0000000a, /* MC_EMEM_ARB_CFG */
0x00000014, /* MC_EMEM_ARB_CFG */
0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
0x00000004, /* MC_EMEM_ARB_TIMING_RP */
Expand Down Expand Up @@ -1514,24 +1514,24 @@ int grouper_emc_init(void)
printk("grouper_emc_init:mem_bootstrap_ad4=%u mem_bootstrap_ad5=%u \n",mem_bootstrap_ad4,mem_bootstrap_ad5);

if(!mem_bootstrap_ad4 && !mem_bootstrap_ad5){
tegra_init_emc(Nakasi_dvfs_Elpida_table_0430,
ARRAY_SIZE(Nakasi_dvfs_Elpida_table_0430));
printk("grouper_emc_init:Nakasi_dvfs_Elpida_table_0430\n");
tegra_init_emc(Nakasi_dvfs_Elpida_table_0704_15R7,
ARRAY_SIZE(Nakasi_dvfs_Elpida_table_0704_15R7));
printk("grouper_emc_init:Nakasi_dvfs_Elpida_table_0704_15R7\n");
}else{
tegra_init_emc(Nakasi_dvfs_Hynix_table_0430,
ARRAY_SIZE(Nakasi_dvfs_Hynix_table_0430));
printk("grouper_emc_init:Nakasi_dvfs_Hynix_table_0430\n");
tegra_init_emc(Nakasi_dvfs_Hynix_table_0704_15R7,
ARRAY_SIZE(Nakasi_dvfs_Hynix_table_0704_15R7));
printk("grouper_emc_init:Nakasi_dvfs_Hynix_table_0704_15R7\n");
}

return 0;

err_handle:
if(tegra_init_emc(Nakasi_dvfs_Elpida_table_0430,
ARRAY_SIZE(Nakasi_dvfs_Elpida_table_0430))){
printk("[unknow bootstrap pin] use Nakasi_dvfs_Elpida_table_0430\n");
}else if (tegra_init_emc(Nakasi_dvfs_Hynix_table_0430,
ARRAY_SIZE(Nakasi_dvfs_Hynix_table_0430))){
printk("[unknow bootstrap pin] use Nakasi_dvfs_Hynix_table_0430 \n");
if(tegra_init_emc(Nakasi_dvfs_Elpida_table_0704_15R7,
ARRAY_SIZE(Nakasi_dvfs_Elpida_table_0704_15R7))){
printk("[unknow bootstrap pin] use Nakasi_dvfs_Elpida_table_0704_15R7\n");
}else if (tegra_init_emc(Nakasi_dvfs_Hynix_table_0704_15R7,
ARRAY_SIZE(Nakasi_dvfs_Hynix_table_0704_15R7))){
printk("[unknow bootstrap pin] use Nakasi_dvfs_Hynix_table_0704_15R7\n");
}else
printk("grouper_emc_init:no validate EMC tabe, disable EMC DVFS\n");
return 0;
Expand Down

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