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[Refactor] kernels: Centralize GPU architecture queries in sglang.kernels.arch - #47782

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BBuf merged 6 commits into
sgl-project:mainfrom
DarkSharpness:kernels-arch
Nov 2, 2026
Merged

BBuf merged 6 commits into
sgl-project:mainfrom
DarkSharpness:kernels-arch

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@DarkSharpness DarkSharpness commented Nov 1, 2026 •

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(auto generated by Claude)

Motivation

Kernels query GPU architecture in many ad-hoc ways: torch.cuda.get_device_capability(...), get_device_properties(...).multi_processor_count, gcnArchName string checks, sglang.srt.utils helpers, and the JIT compile target get_jit_cuda_arch(), which several kernels also used for runtime decisions. These are duplicated, sometimes hard-code device 0, and make sglang.kernels depend on sglang.srt.

This PR adds one self-contained entry point, sglang.kernels.arch.current_arch(), and moves kernel arch queries onto it.

Modifications

  • New sglang.kernels.arch (torch only, no srt dependency):
    • current_arch() returns a process-wide cached object chosen from PlatformInfo.detect(): CudaArch on NVIDIA, HipArch on AMD, a plain DeviceArch elsewhere. All GPUs in a node are assumed to be the same model, so there is no device argument. Attributes are cached_property, read lazily on first use.
    • Shared: num_sms, warp_size, l2_cache_bytes, smem_per_block_optin, smem_per_sm, regs_per_sm, max_threads_per_sm, name, props, supports_pdl.
    • is_sm(major, minor=None) / is_sm_at_least(major, minor=0): False off NVIDIA, so call sites need no platform guard.
    • .cuda / .hip narrow to the platform object (None elsewhere). CudaArch adds major, minor, capability, sm_version, max_vec_bytes, supports_cluster; HipArch adds gcn_arch.
  • PlatformInfo.detect() is now cached (_probe() is the uncached probe) and gains is_hip / is_musa; the selector drops its own lru_cache.
  • JIT compile target: ArchInfo is renamed to CompileArch (a frozen msgspec.Struct). get_jit_cuda_arch() becomes the internal get_compile_arch() used only by the build pipeline, and make_jit_cuda_arch() becomes CompileArch.for_capability(). override_jit_cuda_arch() is removed (its only user compiled for the local GPU anyway). is_arch_support_pdl() reads current_arch().supports_pdl, and is_hip_runtime() / is_musa_runtime() read PlatformInfo.
  • About 80 call sites in sglang.kernels (plus a few kernel tests and benchmarks) now use current_arch() instead of direct torch/srt queries. Several one-line local helpers (_num_sms, _get_num_sm, _mla_core_count, ...) are removed.

Left unchanged on purpose: vendored code (flash_attn/cute, fla, code ported from vLLM/aiter/FlashInfer/CUTLASS), import-time queries, srt predicates that also gate on the CUDA toolkit version (is_sm100_supported, ...), AMD family predicates (is_gfx95_supported, ...), and sites that rely on ROCm reporting gfx-derived capabilities. These can follow once the matching interfaces exist.

Behavior notes:

  • Kernel helpers that took a device argument for an arch query now ignore it (same-model assumption). The parameters are kept to avoid touching callers.
  • CUDA-only paths that used to compare ROCm's gfx-derived capability now treat ROCm as "not NVIDIA".

Accuracy Tests

No numerical change: the patch only changes how architecture facts are read.

Speed Tests and Profiling

N/A.

Checklist

🤖 Generated with Claude Code


CI States

Latest PR Test (Base): ❌ Run #41361360932
Latest PR Test (Extra): ❌ Run #41361360833
Latest PR Test (AMD ROCm 10): ❌ Run #41361360820

Tip

Base CI only covers the core cases, and its workload may not exercise your change. Use /rerun-test to run the tests your change touches, or copy this prompt for an agent:

Find the registered tests this PR affects and run them with /rerun-test, following https://github.com/sgl-project/sglang/blob/main/.agents/skills/rerun-test/SKILL.md

DarkSharpness and others added 3 commits November 1, 2026 10:34
…nels.arch

Add sglang.kernels.arch.current_arch(), a cached per-process CudaArch / HipArch / DeviceArch object with lazy device attributes (num_sms, shared memory, L2, capability, is_sm / is_sm_at_least, supports_pdl), and move kernel arch queries onto it. Cache PlatformInfo.detect(). Rename the JIT compile target ArchInfo to CompileArch, make get_jit_cuda_arch an internal get_compile_arch, and drop override_jit_cuda_arch.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

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Claude Code Review

This pull request is from a fork — automated review is disabled. A repository maintainer can comment @claude review to run a one-time review.

@github-actions github-actions Bot added quant LLM Quantization amd lora hicache Hierarchical Caching for SGLang blackwell SM100/SM120 jit-kernel labels Nov 1, 2026
@DarkSharpness DarkSharpness added the run-ci CI: run the baseline test suite on this PR label Nov 1, 2026
@github-actions github-actions Bot added the documentation Improvements or additions to documentation label Nov 1, 2026
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ping @BBuf (or his/her agent) for review

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/rerun-test test/registered/kernels/ops/gemm/test_cutedsl_dual_gemm.py

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github-actions Bot commented Nov 1, 2026 •

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🚀 4-gpu-b200 (1 test): ✅ View workflow run

cd test/ && python3 registered/kernels/ops/gemm/test_cutedsl_dual_gemm.py

# Conflicts:
#	python/sglang/kernels/ops/moe/moe_fused_gate.py

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LGTM. The earlier hardware-validation request remains open.

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BBuf commented Nov 2, 2026

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/rerun-failed-ci

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BBuf commented Nov 2, 2026

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[BBuf Review Agent] @DarkSharpness these CI failures look related to this change, could you take a look?

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(auto generated by Claude)

@BBuf this one is pre-existing on main, not from this change. TestDisaggFlux3Image.test_t2i_and_edit_match_monolithic fails in multimodal-gen-test-2-gpu-amd (0) on every recent scheduled pr-test-amd.yml run on main, with the same signature:

It has failed this way since 10-29. The open fix is #46947 (deterministic VAE convolutions on ROCm).

The CUDA side of this PR is blocked by two other main-side failures in multimodal-gen-unit-test: test_cfg_parallel_warmup.py::test_bcg_default_resolution_of_two_stage_is_the_output_resolution (#47474's test vs #47582's fallthrough for unaligned two-stage defaults) and test_fused_lora_compose.py::test_alpha_override_reloads_fused_sections (/adapter not found, added by #46255). /rerun-failed-ci reuses the old merge SHA, so it cannot pick up a main fix; I'll push a fresh merge once those land.

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BBuf commented Nov 2, 2026

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[BBuf Review Agent] @DarkSharpness The test and VAE code match main, and the changed Flux3 PrimsTS path is still CUDA-only. I'll drop the AMD CI attribution.

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BBuf commented Nov 2, 2026

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/rerun-failed-ci

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BBuf commented Nov 2, 2026

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/rerun-failed-ci

@BBuf
BBuf merged commit a133231 into sgl-project:main Nov 2, 2026
522 of 571 checks passed
@DarkSharpness
DarkSharpness deleted the kernels-arch branch November 2, 2026 10:58
rohithrr9 added a commit to rohithrr9/sglang that referenced this pull request Nov 2, 2026
Main removed get_jit_cuda_arch (sgl-project#47782), so the SM10x checks of the W8A16 path
(dsv3_fused_a_gemm_fp8_module, the cuda_sm10x test fixture, benchmark_fp8) now
use current_arch().is_sm(10).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Yuxingwang-intel pushed a commit to Yuxingwang-intel/sglang that referenced this pull request Nov 6, 2026
…nels.arch (sgl-project#47782)

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
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amd blackwell SM100/SM120 documentation Improvements or additions to documentation hicache Hierarchical Caching for SGLang jit-kernel lora quant LLM Quantization run-ci CI: run the baseline test suite on this PR

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