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[diffusion] perf: pipeline MiniMax-H3's Ulysses exchange against attention over the copy engine - #43164
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…ntion over the copy engine MiniMax-H3's Ulysses exchange around dense attention runs on SMs (an NCCL send/recv for q/k/v, SM copies back), between kernels that keep every SM busy. This adds an opt-in copy-engine transport for same-host Ulysses groups of any size and uses it to pipeline the exchange against attention over head groups: group g's q/k/v copies run on the copy engine while group g-1 attends, each group attends on its own stream and sends its output from there, and stream memory operations order copies and kernels without holding an SM. - SGLANG_DIFFUSION_ULYSSES_PIPELINE_GROUPS=<G> pipelines MiniMax-H3's dense FA attention; G must divide the heads per rank. - SGLANG_DIFFUSION_IPC_A2A_MULTI=1 also routes the plain Ulysses all-to-all through the copy engine. - Falls back to the sequential exchange when a rank lacks peer access or stream memory operations (agreed across the group), during graph capture, under torch.compile, and for other attention backends. The result is bit-identical to the sequential exchange; a 2- and 4-rank test checks it byte for byte. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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… Ulysses exchange Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…put as it arrives Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…here it fits Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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…he 2-GPU suite Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Motivation
With Ulysses, every MiniMax-H3 block exchanges q/k/v before dense attention and the output after it. Both exchanges run on SMs: an NCCL send/recv for q/k/v, and SM copies for the output. They sit between kernels that keep every SM busy (FlashAttention is ~63% of a denoise step on 2×H200), so their time is fully exposed.
Modifications
Four commits. Each one is bit-identical to the sequential exchange.
Copy-engine all-to-all with head-group pipelining (
ipc_a2a_multi.py,_minimax_h3_pipelined_dense_attention).ipc_a2adesign widened to N same-host ranks: each rank writes its chunk straight into its peers' staging buffers with device-to-device copies on the copy engine, and a per-peer sequence flag orders data before flag.cuStreamWriteValue32/cuStreamWaitValue32) order copies and kernels without holding an SM.torch.compile, and for other attention backends, VSA and ring.QK-norm + RoPE writes straight into the exchange. The out-of-place QK-norm kernel writes each destination block's normalized q/k, plus v, in place of the in-place norm followed by a pack. Blocks for this rank go straight into its own receive slot, so they skip a device-to-device copy. Groups are produced in order, so the norm of later groups overlaps the attention of earlier ones.
Each head group is merged into the output as it arrives. Group streams write this rank's rows, and then each peer's, directly into the final tensor. This replaces the trailing merge kernel and the own-rank output copy.
On by default.
SGLANG_DIFFUSION_ULYSSES_PIPELINE_GROUPSnow defaults to-1:0disables it, andN ≥ 2forces N groups.SGLANG_DIFFUSION_IPC_A2A_MULTI(the plain all-to-all over the copy engine) stays opt-in. The cookbook's configuration notes describe the default.Accuracy Tests
python/sglang/multimodal_gen/test/single_test_file/test_ipc_a2a_multi_gpu.py(new; passes at 2 and 4 ranks on the final commit) checks, byte for byte:Unrelated to this PR:
test_ipc_a2a_2_gpu.pyfails the same way on plain main ("AllToAll4D never took the IPC path").Speed Tests and Profiling
Client end-to-end latency, 4×H200, 50 steps,
--performance-mode speed, eager, median of 2 requests, G=7. Arms are interleaved on one box: adjacent columns ran back to back. The box drifts ~0.3% across sessions, so compare within a row only.4: on by default. With no environment variable set, the pipeline picks G=7 and runs as fast as the explicit G=7 arms: T2VA Ulysses 2 141.27 s (141.33 s with G=7), Ulysses 4 72.20 s (72.23 s). Outputs are md5-equal to main.
All four commits against main, one interleaved pass, no env: T2VA Ulysses 2 144.80 → 141.32 s (−2.4%), Ulysses 4 74.19 → 72.23 s (−2.6%). For Ref2VA the chain of paired steps above gives about −1.7% on top of [diffusion] perf: decode plain base64 MiniMax-H3 materials without a per-character loop #43117.
Per-layer budget, Ref2VA at Ulysses 2 after commit 1 (ms): wall 88.38, made up of the compute union 87.45, exposed exchange 0.58 and idle 0.36. The copy engine moves 2.53 ms/layer underneath the attention.
Why the gains are below the exposed time: the H200s sit at their 700 W cap during denoise, so part of the freed SM time comes back as a lower clock.
Checklist
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CI States
Latest PR Test (Base): ✅ Run #37897253385
Latest PR Test (Extra): ❌ Run #37897253153
Latest PR Test (AMD ROCm 10): ❌ Run #37897253236