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[diffusion] CI: fix qwen cache-dit step 10/49 perf baselines - #42495

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mickqian merged 4 commits into
sgl-project:mainfrom
niehen6174:fix/ltx25-ci-resident
Oct 7, 2026
Merged

mickqian merged 4 commits into
sgl-project:mainfrom
niehen6174:fix/ltx25-ci-resident

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@niehen6174

@niehen6174 niehen6174 commented Oct 4, 2026 •

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Motivation

qwen_image_t2i_cache_dit_enabled fails its H100 per-step perf check at random. From 09-30 to 10-04, 71% of attempts went over the step-49 limit. Every final 1-GPU failure in that window came from this case.

The cause, found in the debug runs in #42546, is how the step time is measured. It is not a regression.

  • Steps 10 and 49 are the first cached step after a full step.
  • Per-step times are host wall times with no device sync.
  • The cache-dit residual check in that step is the first point where the host blocks, so that step absorbs the previous full step's queued GPU work.

Debug run on CI H100, 3 launches per arm, times in ms:

Arm Full step Steps 10 / 49 Other cached steps E2E
Fused QK-norm/RoPE epilogue on, unsynced (CI today) 178 64 / 66 6.3 4310
Fused off, unsynced 196 55 / 56 6.5 4455
Fused on, SGLANG_DIFFUSION_SYNC_STAGE_PROFILING=1 238 7.0 / 7.1 6.3 —
Fused off, synced 245 7.2 / 7.1 6.5 —

With synced timing, steps 10 and 49 take about 7 ms, like every other cached step. #38584 enabled the fused epilogue on Hopper, which cut host launches from 3031 to 2007 per profiled window. The real GPU time got about 3% faster. But the host now enqueues faster too, so more GPU work spills into steps 10 and 49.

Modifications

perf_baselines/h100.json: steps 10 and 49 of qwen_image_t2i_cache_dit_enabled are set to their CI medians, 64.58 / 66.38 ms (previously 48.7 / 45.11). The medians come from 328 H100 CI measurements between 09-30 and 10-04. They are the unsynced host wall times this check measures. No other baseline or tolerance changes.

The ltx_2_5_diffusion_decoder_2gpus timing tolerance from earlier commits is dropped. Its host-bound slowdown will be handled in a separate PR.

Validation

PR CI on fe3b48d passed with the same qwen baselines.

🤖 Generated with Claude Code


CI States

Latest PR Test (Base): ✅ Run #37476814004
Latest PR Test (Extra): ❌ Run #37476813352
Latest PR Test (AMD ROCm 10): ❌ Run #37476814266

…tep baselines

- ltx_2_5_diffusion_decoder_2gpus: component-offloading the DiT made denoise
  randomly 1.4-1.9x slower per server launch. Keep the DiT and text encoder
  resident and re-baseline the case from resident CI runs.
- qwen_image_t2i_cache_dit_enabled: steps 10 and 49 are first cached steps
  (~65 ms on every H100 runner); set them to the CI median.
@niehen6174 niehen6174 added diffusion SGLang Diffusion run-ci CI: run the baseline test suite on this PR labels Oct 4, 2026
…ts timing tolerance

The case exists to cover the offloaded DiT, so restore its original residency and baselines. Denoise is randomly 1.4-1.9x slower per launch with the DiT offloaded; a 1.0 timing_tolerance keeps the case green until that is fixed. The qwen cache-dit step 10/49 baseline fix is unchanged.
@niehen6174 niehen6174 changed the title [diffusion] CI: run ltx_2_5 decoder resident and fix qwen cache-dit step baselines [diffusion] CI: widen ltx_2_5 decoder timing tolerance and fix qwen cache-dit step baselines Oct 4, 2026
@niehen6174
niehen6174 marked this pull request as draft October 4, 2026 15:30
@niehen6174
niehen6174 marked this pull request as ready for review October 5, 2026 07:59
The ltx_2_5 host-bound slowdown will be handled in a separate PR; this PR now only fixes the qwen cache-dit step 10/49 baselines.
@niehen6174 niehen6174 changed the title [diffusion] CI: widen ltx_2_5 decoder timing tolerance and fix qwen cache-dit step baselines [diffusion] CI: fix qwen cache-dit step 10/49 perf baselines Oct 6, 2026
@mickqian
mickqian merged commit 6da08fd into sgl-project:main Oct 7, 2026
135 of 142 checks passed
cursor Bot pushed a commit to cipheraxat/sglang that referenced this pull request Oct 9, 2026
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