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[DSV4] Reserve the FULL logical page in the c4 indexer pool like its KV pool - #41163
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hnyls2002 merged 1 commit intoOct 1, 2026
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…KV pool sgl-project#39921 sized the compressed KV sub-pools with _num_dsv4_physical_kv_pages, which reserves one FULL logical page (ratio physical pages) for the allocator's dummy page. The c4 lightning-indexer pool kept the old (size + page_size + 1) // page_size count, so the PD entries registered by get_contiguous_buf_infos no longer share one page count: on the flash layout (ratios 4/128, page 256) rows per entry went from 33 everywhere to 36 (c4 KV) / 33 (c4 indexer) / 160 (c128 KV). The NIXL connector prepares one destination descriptor list per registered entry from the slot count the decode advertises for entry 0 (the c4 KV page count). The indexer entries are three pages shorter than that, the descriptors walk past their registered region, and the prefill dies with NIXL_ERR_NOT_FOUND in _prep_equal_tp_dlist. Mooncake does not prebuild full-range lists and is unaffected. Give DeepSeekV4IndexerPool the same global_page_size as DeepSeekV4SingleKVPool and count its pages with the same helper, so the c4 KV and indexer entries are 36/36 again and every entry has at least the c4 KV page count. Without a global_page_size the helper reduces to the old count for page-aligned sizes, so the low-ratio index pools and the NPU packed buffer keep their geometry. The NPU factory accepts the keyword.
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Motivation
Pages per registered entry, flash layout (compress ratios 4/128, page size 256):
Modifications
Accuracy Tests
Not applicable: only reserved pages are added, live page addressing is unchanged.
Speed Tests and Profiling
Not applicable: the indexer pool grows by three 64-token pages per layer at page size 256.
CI States
Latest PR Test (Base): ✅ Run #36097602378
Latest PR Test (Extra): ✅ Run #36097602213
Latest PR Test (AMD ROCm 10): ❌ Run #36097602349