[diffusion] model: support qwen-image-2.1

[mickqian]

Motivation

Add native Qwen-Image 2.1 text-to-image generation and editing, including multiple reference images and RGBA input/output. SGLang owns the model components and preserves the checkpoint's Transformers 4.57.3 conditioning semantics.

Modifications

• Add the DiT, RGBA VAE, Qwen3-VL conditioning, model registration, and CLI/server integration.
• Align conditioning and VAE normalization with Diffusers #14804: training image markers, white alpha compositing for vision only, empty-prompt handling, pre-final-norm text features, and FP32 VAE normalization.
• Integrate request-scoped prefix caching, Cache-DiT, breakable CUDA graphs, TP/Ulysses/Ring/CFG parallelism, encoder sharding, VAE parallel decoding, component/layerwise offload, and adapter mapping.
• Add complex RoPE, Q/K normalization, and scale-only LayerNorm fusions with first-call equality checks and native fallbacks. Detect the running CUDA build's complex multiplication FMA order for Hopper and Blackwell.
• Scope vision RoPE recomputation after device transfers to Qwen-Image 2.1, preserving the existing MiniMax-H3 encoder behavior.
• Add qwen_image21_t2i_tp2 for the two-GPU E2E suite (temporarily disabled until the checkpoint is accessible to fork PR CI): 1024×1024 PNG, 40 steps, CFG 1, seed 42, two consecutive requests, model API and pinned image-consistency checks. Reference image (merged): ci-data-diffusion #7.
• Add unit, CUDA, distributed, and supplemental full-checkpoint HTTP tests; update compatibility/quantization docs and the hardware-aware cookbook command picker.
• Add verified single-RTX PRO 6000 resident/offload recipes and retain non-default picker selections when a shared configuration link is refreshed.

Speed tests

Incremental Q/K normalization on one B200 (resident, FlashAttention, eager, 1024×1024, 40 steps, seed 42, CFG 1; four fresh starts in new/base/base/new order, two warmups per start) reduced median generation latency from 3.114 to 2.828 s (9.17%; 10 samples per variant) and editing from 3.742 to 3.450 s (7.81%; six samples per variant).

The subsequent scale-only LayerNorm change reduced median generation latency from 2.831 to 2.748 s (2.92%) and editing from 3.436 to 3.358 s (2.26%), with identical corresponding output pixels. These measurements predate the latest conditioning correction and apply only to the tested commits/workload; they are not a new accuracy baseline.

On one RTX PRO 6000 Blackwell Server Edition (96GB, SM120), corrected implementation 1eab5de5990 passed 1024×1024/40-step HTTP generation, editing, transparent generation, and repeated transparent-input editing with Torch SDPA. Resident generation/edit medians were 8.23/9.85 s with 40.1 GiB peak device memory; DiT offload measured 10.28/10.66 s and 26.1 GiB. All 13 corresponding RGBA outputs matched exactly across placements; 156 kernel/model tests passed (21 skipped). Multi-GPU and NVFP4 recipes on this GPU remain unverified.

Checklist

Regression validation on two H200 GPUs at 2d7c5365fb0: all 41 focused vision/Qwen tests passed, including exact CPU/GPU RoPE checks and the real component-offload path. Two consecutive H3 ref2va requests produced six sampled frames identical pixel-for-pixel to main 9784d5f979c9; the previous PR head differed on every sampled frame. Both main and the corrected branch remain below the H100 reference-image SSIM threshold on this H200 environment, so this comparison establishes parity with main rather than an upstream H100 consistency pass. Reference images and thresholds are unchanged.

• Format code with pre-commit; validate documentation and links.
• Add unit, distributed, and HTTP tests; retain the temporarily disabled TP2 E2E definition.
• Verify strict RoPE equivalence on Hopper and Blackwell.
• Correct VAE input layout and validate transparent editing against Transformers 4.57.3.
• Complete the corrected-conditioning LayerNorm feature matrix.
• Pass upstream lint with the consolidated kernel-test taxonomy.
• Complete upstream NVIDIA CI.

The TP2 E2E case is temporarily disabled in 6078c9049b3 after upstream CI returned HTTP 401 during checkpoint loading. The case configuration, scheduling estimate, and pinned reference image are retained for re-enabling it when the checkpoint is accessible to fork PR CI. Earlier isolated B200 TP2 consistency tests passed.

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CI States

Latest PR Test (Base): ✅ Run #35448201646
Latest PR Test (Extra): ❌ Run #35448201426
Latest PR Test (AMD ROCm 10): ❌ Run #35448201642