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[AMD] Support DeepSeek-V4.1 on gfx950 with DSpark and fused kernels - #39857

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kevin-mii wants to merge 116 commits into

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kevin-mii:dsv41-amd-main

Commits on Sep 23, 2026
- [AMD] HIP siblings of the DeepSeek V4 JIT kernels and the sorted AOT top-k epilogue
  
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- [AMD] Triton hosts for DeepSeek-V4.1 attention, mHC and decode glue on ROCm
  
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- [AMD] MoE, quantization and GEMM kernels for gfx950
  
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- [AMD] DeepSeek V4 attention on HIP: radix backend, low-ratio indexer, aiter sparse decode
  
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- [AMD] MoE and dense quantization wiring for aiter on ROCm
  
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- [AMD] DeepSeek V4.1 model wiring for HIP: fused mHC boundary, gfx950 dense route, Engram
  
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- Pick the DSA decode graph variant from the DP-group max seq len
  
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- [AMD] ROCm image: aiter pin, FlyDSL stage-1 LDS-DMA drain patch, tuned FMoE rows
  
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- [AMD] Tests: numerics guards on the served shapes and regression tests
  
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- Fix ROCm 10 source pointer types in mHC LDS prefetch
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- [AMD] Integrate dsv4.1 metadata and port KV stores and low-ratio preparation
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- Remove deployment tuning from the AMD runtime change
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- Keep the AMD environment reference update outside this runtime PR
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- Keep the AITER patch compatible with existing whitespace hooks
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- Place MI35x regression tests under the AMD test directory
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- Restore DSV4.1 EP4 FMoE tuning while upstreaming the configuration
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- [AMD] Fuse query RoPE into padded attention output
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- [AMD] Overlap shared Engram lookup and MXFP8 projection
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- [AMD] Use paged FP4 indexing for context-parallel prefill
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- [AMD] Honor fixed context limits in prefill graphs
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- [AMD] Fix DSV4 pool sizing runtime-context lookup
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- [AMD] Support encoder SWA bounded replay on HIP
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- [AMD] Preserve CP token ownership during decoder tail replay
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- Allow decoder tail replay with single-rank DP attention plumbing
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- [AMD] Allow validated V4.1 interleave context parallelism
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- [AMD] Read compact V4.1 FP8 and FP4 KV pages on gfx950
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- [AMD] Prefetch compact KV tiles during attention compute
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- [AMD] Port native 16-head swap-AB attention to gfx950
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- [AMD] Validate DSpark graphs with production communicator warmup
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- [AMD] Accelerate mHC prefill with compensated BF16 projections
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- [AMD] Preserve attention streams so HIP overlap is reachable
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- [AMD] Fuse TP4 attention all-reduce with native mHC post
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- [AMD] Fuse TP4 MoE all-reduce with mHC post
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- [AMD] Tune standalone mHC post for medium prefill batches
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- [AMD] Fix default BF16 SiLU MXFP4 MoE dispatch and clamp
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- [AMD] Avoid BF16 WO-A prefill output layout copies
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- [AMD] Port BF16 WO-A decode and verify projection kernels
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- [AMD] Construct stream test layers on the target device
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- [AMD] Use FP32 weights in the AITER mHC numerical test
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- [AMD] Avoid DSpark sequence-length CPU copies in HIP metadata
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- [AMD] Build EAGLE draft metadata without CPU length mirrors
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- [AMD] Bound the SWA-only draft page-table placeholder
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- [AMD] Preserve BF16 bits when reconstructing sharded Engram rows
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- [AMD] Skip Blackwell norm inspection for pending HIP mHC state
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- [AMD] Test indexer chunking within oversized requests
  
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- Keep HIP BF16x3 prefill opt-in after TP4 throughput regression
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- [AMD] Enable gfx950 V4.1 KV dequantization with exact NaN bits
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- [AMD] Verify C2 padding leaves output and pair state untouched
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- [AMD] Allow Engram prefetch for vision-capable V4.1 checkpoints
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- Describe ROCm support in encoder SWA replay help
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- [AMD] Fuse WO-A verify reduction with native MXFP8 quantization
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- Describe both HIP WO-A operand types in the return contract
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- style: Format the relocated HIP KV-store test decorator
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- test: Preserve compressed KV quantization regressions under AMD
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- Keep HIP WO-A quantization fusion opt-in after serving comparison
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- [AMD] Preserve FP32 scores in the V4 router GEMM fallback
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- [AMD] Reconcile main prefill graphs and updated V4.1 compressor APIs
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- test: Keep mixed CUDA and AMD regressions in the vendor taxonomy
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- style: Format the main rebase compatibility updates
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- test: Update remaining compressor callers and share the KV oracle
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- style: Sort updated quantization test imports
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- [AMD] Pass per-token request mapping to raw verify metadata
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- Trim comments to numerical and graph-lifetime constraints
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- Shorten contracts for routing, graph metadata and kernel dispatch
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- Keep prerequisite-only comments aligned with upstream
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- [AMD] Follow upstream FP4 and mHC module moves
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- [AMD] Include the renamed FP4 indexer header
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- test: Import the candidate reference from its new module
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- style: Format the moved candidate-reference import
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- test: Trim experimental suites and duplicate AMD regressions
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- style: Format the reduced AMD test suites
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- test: Keep focused AMD coverage and reuse existing kernel suites
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- style: Format the focused AMD regression suites
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- test: Limit added compressor and inverse-RoPE cases to AMD
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- test: Place AMD operator suites in kernel subsystems
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- test: Consolidate AMD coverage and remove inadmissible cases
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- ci: Discover AMD kernel suites in existing MI350 jobs
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- style: Format consolidated AMD tests
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- Reconcile AMD DeepSeek-V4.1 tests and kernels with main's module layout
  
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- Keep the ROCm wo_a fast paths independent of fast_path; update AMD tests for main's metadata and KV-config changes
  
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- [AMD] Serve 9-128 verify rows through the direct-output wo_a path
  
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- [AMD] Skip the collapsed-input pre-computation when the fused boundary carries the residual
  
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- [AMD] Accept trailing aiter moe_sorting parameters in the fused sorting probe
  
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- [AMD] Default to adaptive split-KV and native TP4 attention outside deterministic inference
  
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- docs: list the HIP DeepSeek-V4.1 environment variables
  
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- test: consolidate the AMD DeepSeek-V4.1 suites per the admission rule
  
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- Warn when the gfx95 MXFP8 tile table cannot be read
  
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- Rename engram's Triton-kernel gate now that HIP takes it
  
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- Trim the comments around the ROCm mHC fusion and wo_a gates
  
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- test: follow main's parallel-topology validation in the AMD DeepSeek-V4.1 suites
  
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- Drop the unused replay flag from the request-window layout
  
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- test: cut and merge the AMD DeepSeek-V4.1 cases per the admission rule
  
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- test: share one TP4 torchrun across the DeepSeek-V4.1 collectives
  
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- test: cover the ROCm sorting fold-in hand-off on CPU
  
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- test: run the shared DeepSeek-V4.1 kernels on the CUDA lanes too
  
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- Own the ROCm-resolved layer attributes in the model classes
  
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- Read the aiter override arguments without signature.bind per launch
  
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- Drop the unreachable return after the non-low-ratio capture path
  
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- Point the vision top-k gate at its platform-wide branch
  
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- test: estimate the AMD DeepSeek-V4.1 kernel suites from measured runs
  
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- Drop the backticks and Sphinx roles from the branch's Python docstrings
  
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- Apply the code-style review to the AMD DeepSeek-V4.1 port
  
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- Fold the ROCm query rope into the K norm-rope kernel behind a template flag
  
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- Keep one regime in the gfx950 MXFP8 gemv: the waves split K
  
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- Unwrap the gfx950 dense operand once, then dispatch once
  
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- Move the ROCm MoE reduction glue out of deepseek_v2
  
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- Test the trailing aiter sorting parameters by identity
  
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- Keep main's backticks in docstrings the branch only reflowed
  
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- Drop the ROCm env switches and keep the paths they default to
  
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- Read HIP attributes directly and hoist imports that have no cycle
  
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- Restore main's replay floor and drop a call to a missing compressor method
  
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- Move the attention-DP graph-variant sync to its own branch
  
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- Keep main's comments, docstrings and names as main has them
  
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Commits on Sep 24, 2026
- Drop the aiter overrides and keep aiter's own sorting and reduction
  
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- Drop the Docker aiter patches and the DSV4.1 FMoE tuning CSV
  
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- Merge branch 'main' into dsv41-amd-main
  kkHuang-amd
  authored
  e2e824d

Commits

Commits on Sep 23, 2026

Commits on Sep 24, 2026