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AMD-yanfeiwang
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DarkSharpness,
HaiShaw,
HydraQYH,
celve and
yuan-luo
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September 11, 2026 06:28
This was referenced Sep 11, 2026
HaiShaw
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Sep 11, 2026
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Summary
This PR is split from #35233 to keep each change focused and independently reviewable.
It contains only the ROCm-specific HiCache JIT block-quota setting.
Changes
Scope
This PR does not change kernel implementations, memory layouts, backend selection, or registered-host pointer handling.
The registered-host
kernel/page_firstcapability is split into #39041. The complete implementation remains in #35233.Validation
CI States
Latest PR Test (Base): ❌ Run #34570728333
Latest PR Test (Extra): ❌ Run #34570727548
Latest PR Test (AMD ROCm 10): ❌ Run #34570727941