[AMD] [GLM-5.3-Flash Day 0] Enable FP8 and Quark MXFP4 MoE on gfx950

[Raiden-Makoto]

Summary

Replacement for #38037, which GitHub closed when its deleted support base was merged into main.

Replacement for #37629, which was accidentally squash-merged and then reverted by #37880. This reapplies the same reviewed change on the current support-branch head.

GLM-5.3-Flash ships two gfx950 MoE checkpoint paths that share one model architecture but use different quantization contracts:

• zai-org/GLM-5.3-Flash: routed, shared, and MTP experts use block FP8 [128,128] with dynamic FP8 activations.
• amd/GLM-5.3-Flash-Quark-MXFP4: routed and shared experts in layers 3-44 use OCP MXFP4 1×32; MTP layer 45 remains block FP8.

Both paths load gate and up projections into separate contiguous halves and require clamped SwiGLU (swiglu_limit=10.0). The support branch preshuffles the weights but lets AITER infer gate/up semantics from the global interleave setting. Quark also drops clamp/padding metadata and does not make preshuffle ownership explicit.

Contract	Before	With this PR
block-FP8 layout	tile-only preshuffle, no physical layout metadata	records and forwards GateMode.SEPARATED
Quark MXFP4 layout	global interleave default can override checkpoint ordering	pins separated mode; AITER preserves explicit quant-method mode
SwiGLU	FP8 forwards the limit; Quark omits it	both forward swiglu_limit=10.0
preshuffle	Quark can preshuffle without owning the selected runner	requires an owned AITER runner
unsupported Quark runner	fails later with an unset runner	fails during construction
padding	Quark padding is not forwarded	hidden/intermediate padding is recorded and forwarded

Scope

Five production files:

• fp8.py: preserve separated gate/up layout and forward block-FP8 clamp, scale, and padding metadata.
• quark_w4a4_mxfp4_moe.py: own AITER preshuffle and forward MXFP4 clamp/layout/padding metadata.
• aiter.py: preserve an explicitly selected gate mode.
• quark.py: map per-layer Quark configuration names and dispatch serialized block-FP8 linear/MoE layers through the existing FP8 methods.
• glm5_next.py: map Flash checkpoint names, including block-FP8 weight_scale to runtime weight_scale_inv.

Five test files cover CPU contracts, model-name/scale mapping, synthetic gfx950 numerics, and both real checkpoints. DSA, k-pool, MLA, mHC backend selection, CUDA graphs, EP/A2A, and scheduler policy are unchanged.

PR boundary: #39317 exclusively owns direct fused-module and per-expert Quark exclude handling in quark/utils.py. This PR no longer modifies that file or test_quark_utils.py. Full amd/GLM-5.3-Flash-Quark-MXFP4 serving requires both changes; they no longer duplicate code.

Test plan

Combined main-based integration (RM/glm53-day0-main-integration @ 22f233a853) on 4x MI355X/gfx950 using rocm/sgl-dev:v0.5.19-rocm724-mi35x-20260910:

• amd/GLM-5.3-Flash-Quark-MXFP4@b5688f2549: 20/20 GSM8K (100.00%), 100.00% stop rate, zero truncations/errors.
• zai-org/GLM-5.3-Flash@03eb536628 block FP8: 19/20 GSM8K (95.00%), 100.00% stop rate, zero truncations/errors.
• Both checkpoints loaded all 62 shards, completed decode graph capture, and returned a correct stopped generation for 17 + 25 (42).

Recovery validation:

• scoped pre-commit passed;
• Quark mixed-precision configuration: 18 tests passed;
• GLM block-FP8 scale-name mapping: 1 test passed;
• existing MoE CPU, gfx950 synthetic, and checkpoint contracts remain covered by this PR.

Checkpoint exclusion behavior is intentionally tested in #39317, not duplicated here.

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CI States

Latest PR Test (Base): 🚫 Run #34794563024
Latest PR Test (Extra): ❌ Run #34794562943
Latest PR Test (AMD ROCm 10): ❌ Run #34794562968

[Raiden-Makoto]

/rerun-failed-ci

[Raiden-Makoto]

/rerun-failed-ci