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Motivation
GLM-5.3-Flash's NextN draft shares the target's hybrid request pool. PD decode adds preallocation slots beyond
max_running_requests, but the plain DSA builder uses that running limit to size compression tails indexed byreq_pool_idx.With 32 running requests and 64 extra slots, slot 96 is valid but the tail has only 33 rows:
The same model's target hybrid branch already sizes tails from the actual request table. The plain draft branch missed this distinction. Graph replay also preserves these request IDs.
Modifications
req_to_token_pool.req_to_token.shape[0]asmax_running_requests, matching the target hybrid branch. Keep the existing parameter name, function signature and constructor+1; the scheduler's running limit stays unchanged.Accuracy Tests
The results below were collected at
7f66f7e5afwithshape[0] - 1. This revision aligns with the target hybrid branch by usingshape[0], allocating one additional row; runtime tests were not rerun. No new UT is included.assert torch.Size([33, 6, 128]) == (97, 6, 128); 4 failurestorch._dynamo.exc.InternalTorchDynamoError: AcceleratorError: CUDA error: an illegal memory access was encounteredThe regression uses a controlled restoration of the old capacity. Serving used TileLang/BF16, TP8/EP8, EAGLE 1/1/2, Prefill eager and Decode full Graph. Prefill draft Graph still has the separate width issue in #37573. No model-quality benchmark was run.
Deployment commands and full earlier error
Deploy and use
Use an SGLang installation containing this PR, with GLM-5.3-Flash and a working Mooncake/RDMA setup. Start two workers with 8 GPUs each, followed by the router. Set the model path, reachable worker/router addresses and RDMA device list for your deployment. The router needs access to the model configuration as well. Allow the Prefill HTTP/bootstrap ports (32171/28998), Decode HTTP port (32172), and router port (30000) between the relevant components.
Prefill
Decode
Router
Send a request
Once both workers and the router are ready, send a request to the router's OpenAI-compatible endpoint:
Full error before the fix
One complete TP0/EP0 traceback from the earlier
dcebe8cPD eager baseline. Checkout/install path prefixes and the timestamp are normalized; all stack frames and the final error are retained.Speed Tests and Profiling
Not run; this is an allocation-correctness fix, with no performance claim.
Checklist
Review and Merge Process
Awaiting review and CI; the PR remains a draft.
CI States
Latest PR Test (Base): ⏳ Run #34206300050
Latest PR Test (Extra): ❌ Run #34206299712
Latest PR Test (AMD ROCm 7.2): ⏳ Run #34206300540