[AMD][Diffusion] FlyDSL fused norm kernels on wave32 targets (gfx1250)

[yctseng0211]

Motivation

Applies on top of #36349 (FlyDSL v0.3.0 stable-API migration).

Problem

SGLANG_USE_ROCM_FLYDSL=1 aborts at kernel compile time on gfx1250 (MI450):

LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.permlane32.swap

This is not a regression from #36349 -- the pre-migration kernel fails
identically. Both versions carry the same wave64 assumption.

Root cause

fused_residual_norm_flydsl.py hardcodes WARP_SIZE = 64 and
_SHUFFLE_OFFSETS = (32, 16, 8, 4, 2, 1). gfx1250 is a wave32 part
(torch.cuda.get_device_properties().warp_size == 32), so the leading stride-32
XOR shuffle of width 64 crosses the wave boundary. The lowering can only express
that as permlane32_swap, which exists only in the wave64 ISA, so instruction
selection fails.

Fix

Derive the three wave-dependent constants from the device warp size:

• WARP_SIZE from torch.cuda.get_device_properties().warp_size, falling back
  to 64 when no device is visible.
• _NUM_WAVES from a fixed 640-thread block, so BLOCK and the public
  FLYDSL_NORM_MIN_ALIGNED_DIM (5120) stay identical on both wave sizes and
  callers are unaffected.
• _SHUFFLE_OFFSETS starting at WARP_SIZE // 2.

No other change is needed: both reduction sites go through wave_reduce_add,
which already iterates len(_SHUFFLE_OFFSETS).

On wave64 every derived value is identical to before (_NUM_WAVES = 10, offsets
(32, 16, 8, 4, 2, 1)), so gfx950 codegen is unchanged.

Validation

gfx1250 (MI450), ROCm 10, Wan2.2-T2V-A14B, 480x832, 33 frames, 4 steps,
HIP_FORCE_DEV_KERNARG=0:

	FLYDSL=0	FLYDSL=1 before	FLYDSL=1 after
result	ok	LLVM ERROR	ok
latent neighbour corr (w/h/frame)	.9433 / .9020 / .9488	--	.9430 / .9064 / .9494
latent corr vs FLYDSL=0	--	--	0.9778
denoise	8.95 s/step	--	8.48 s/step

Structural metrics match the FLYDSL=0 reference to within 0.005 (pure noise
scores ~0.001 on the same metric) and the decoded video is visually
indistinguishable. The residual latent difference is the expected bf16 rounding
drift from a different reduction order, and it grows with step count as it
accumulates -- at 17 frames / 2 steps the same comparison gives 0.9991.

Note for reviewers

FlyDSL 0.3.1 separately misclassifies gfx1250 as CDNA: is_rdna_arch() only
matches the gfx10 / gfx11 / gfx120 prefixes, so gfx1250 falls through and
gets warp_size = 64 plus a wave64 = true compile target. That does not block
this fix -- verified by A/B running with and without a shim that corrects the
classification, both produce correct output -- but the same predicate also
drives buffer descriptor flag selection, so it is worth fixing upstream.

Modifications

Accuracy Tests

Speed Tests and Profiling

Checklist

• Format your code according to the Format code with pre-commit.
• Add unit tests according to the Run and add unit tests.
• Update documentation according to Write documentations.
• Provide accuracy and speed benchmark results according to Test the accuracy and Benchmark the speed.
• Follow the SGLang code style guidance.

Review and Merge Process

1. Ping Merge Oncalls to start the process. See the PR Merge Process.
2. Get approvals from CODEOWNERS and other reviewers.
3. Trigger CI tests with comments or contact authorized users to do so.
   • Common commands include /tag-and-rerun-ci, /tag-run-ci-label, /rerun-failed-ci
4. After green CI and required approvals, ask Merge Oncalls or people with Write permission to merge the PR.

---

CI States

Latest PR Test (Base): ❌ Run #34829420545
Latest PR Test (Extra): ❌ Run #34829420101
Latest PR Test (AMD ROCm 10): ❌ Run #34829420138

[yctseng0211]

https://github.com/sgl-project/sglang/actions/runs/33733102952

[yctseng0211]

https://github.com/sgl-project/sglang/actions/runs/33733102952

[HaiShaw]

/tag-and-rerun-ci

[yctseng0211]

@HaiShaw
it's amd specific change, also verified on gfx1250, safe to merge.
Cc: @bingxche

[yctseng0211]

https://github.com/sgl-project/sglang/actions/runs/33733102952

CI passed