[ROCm] Enable shfl xor sync style reduce on amd - #3701
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yiakwy-xpu-ml-framework-team wants to merge 11 commits into
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yiakwy-xpu-ml-framework-team wants to merge 11 commits into
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February 19, 2025 13:35
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Sep 7, 2026
init_fi_a2a_workspace() rejected every device whose is_mnnvl_fabric_supported() is False, i.e. every Blackwell box without an IMEX/NVL72 fabric (x86 B200/B300), even though FlashInfer can serve that case: since 0.6.16 (flashinfer sgl-project#3701) MnnvlMemory exports the workspace with POSIX file-descriptor handles and exchanges them over AF_UNIX SCM_RIGHTS, which needs no CAP_SYS_PTRACE. sglang pins FlashInfer 0.6.18, so the only remaining requirement is that the DCP group is contained in one node.
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Motivation
This is follow up of PR#3664
Modifications
Checklist