[AMD] Add Qwen3.8-Flash-Next-FP8 nightly validation on ROCm 7.2 (verified on rocm720) - #36901
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The AMD rows point at lmsysorg/sglang-rocm:qwen38flashnext, which is a container snapshot rather than a build of docker/rocm.Dockerfile. Its SGLang tree is a copy of #36497 taken before that PR grew the FP8 PLE weight-scale path, so the FP8 checkpoint aborts during weight load with an ngram_embedding.weight_scale assertion (#36616). The only accuracy run recorded in that image is BF16 at TP8, so the FP8 cells were claiming a verification that does not exist. Mark the two AMD FP8 cells in-progress with the reason, and document the docker/rocm.Dockerfile build that reproduces the image from a chosen revision. Co-authored-by: quitenode <quitenode@users.noreply.github.com>
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Signed-off-by: andyluo7 <andy.luo@amd.com>
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The checkpoint declares model_type "qwen4_exp", which AutoConfig only resolves once sglang.srt.configs.Qwen4ExpConfig exists. On a build without it the nightly job dies at server launch with ValueError: The checkpoint you are trying to load has model type `qwen4_exp` but Transformers does not recognize this architecture which is a missing dependency, not an accuracy regression. Guard the test class so the job reports a skip with that reason and starts gating on its own once the model-support PR lands. Co-authored-by: quitenode <quitenode@users.noreply.github.com>
…8-flash-next-rocm-image-fe21 Co-authored-by: quitenode <quitenode@users.noreply.github.com>
…ts FP8 gap" This reverts commit d124727.
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…e21 (includes #37500 Qwen3.8-Flash-Next model support) Co-authored-by: Michael <michaelzhang-ai@users.noreply.github.com>
Drop the Qwen4ExpConfig skip guard. Model support is on main, so the GSM8K nightly should run rather than skip. Co-authored-by: Michael <michaelzhang-ai@users.noreply.github.com>
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September 9, 2026 00:38
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Update after #37500 merged (2026-09-08)
Still a follow-up, not this diff: #36601 Previous rocm720 MI35x wiring proof: https://github.com/sgl-project/sglang/actions/runs/33215101724 (skipped because model support was not on |
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Motivation
Add the AMD nightly accuracy gate for
Qwen/Qwen3.8-Flash-Next-FP8on ROCm 7.2.The generic model (
qwen4_exp/Qwen4ExpConfig) landed in #37500 (2026-09-08), which closed/superseded #36497. This branch is merged onto currentmainand the skip guard is gone, so the nightly runs GSM8K instead ofOK (skipped=1).Two jobs, matching the two topologies the released FP8 checkpoint needs — gfx942 cannot hold target + MTP draft + graph/KV state on one GPU, gfx950 can:
nightly-2-gpu-mi30x-qwen38-flash-next-fp8-rocm720linux-mi300-2gpu-sglangmem-fraction-static0.75nightly-1-gpu-mi35x-qwen38-flash-next-fp8-rocm720linux-mi35x-gpu-1mem-fraction-static0.95Both exercise the AITER decode-graph path with EAGLE speculation (3 / 1 / 4) against a pinned checkpoint revision, gated on GSM8K ≥ 0.94 plus a multimodal smoke check. Direct AITER paged QSA stays disabled so the correctness gate does not depend on an unreleased AITER API.
Modifications
CI only — two files.
[AMD] Add Qwen3.8 Flash Next nightly validation— cherry-picked from [AMD] Support Qwen3.8-Flash-Next MXFP4 on ROCm #36601 (3003ddf15), authorship preserved. Adds the two workflow jobs tonightly-test-amd-rocm720.ymlandtest/registered/amd/accuracy/test_qwen38_flash_next_fp8_eval.py. Suites are registered in the test file viaregister_amd_ci, so notest/run_suite.pychange is needed.origin/main— picks up support qwen 3.8 flash next #37500 (Qwen4ExpConfigand the QSA/PLE stack).Qwen4ExpConfigskip guard that existed only while model support was missing.Net diff against
mainis those two files.Remaining follow-up (not this PR)
The suite is fully on the intended AITER MoE path once #36601's
619632b2c("Honor explicit AITER MoE backend selection") lands. This test uses--moe-runner-backend aitertogether withSGLANG_USE_AITER=0. Until that restack, the CLI flag may not independently select AITER MoE.NVIDIA QSA follow-ups (#36644 FP8 KV, #36556 SM12x) are not ROCm blockers. Issue #36616 remains an image-rebuild item, not a missing code change.
Accuracy Tests
Wiring was verified on the rocm720 flavor before #37500, with
job_selectnarrowed to the MI35x job:KeyError: 'qwen4_exp'OK (skipped=1))main09a9efb0fOK (skipped=1))Those runs prove checkout, VRAM clear, ROCm 7.2.0 container setup, dependency install, HF cache, suite resolution, and server CLI. They could not score GSM8K because
qwen4_expwas not onmain.This update: skip guard removed; current head
31de6319deincludes #37500. A new MI35xjob_selectdispatch is needed to record a real GSM8K number. For reference, #36601 reports GSM8K 96.80% on gfx950 FP8 TP1 and 96.96% on gfx942 FP8 TP2/EP2 for this path.Not verified in the old runs: the
rocm724matrix flavor, the 2-GPU MI30x job.Local checks: both jobs are defined, land on the right runners, appear in the
job_selectoptions, self-match their ownifgate, and are wired intocheck-all-jobs.needswithout dropping any job that is already onmain; the two suite names the workflow invokes are exactly the two the test file registers.Speed Tests and Profiling
Not applicable — CI-only change.
Checklist
CI States
Latest PR Test (Base): ❌ Run #34829340183
Latest PR Test (Extra): ❌ Run #34829339697
Latest PR Test (AMD ROCm 10): ❌ Run #34829340008