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[AMD] Optimize Kimi-K3 Triton MLA prefill on gfx950 - #35770
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Convert row and column indices to int64 for compatibility.
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Hi, @clintg6 In long-context cases (chunk-prefill or radix-cache on), the prefix sweep dominates Based on your PR, I added the change here. Both the radix-cache-on and the chunked-prefill paths benefit. Test Config: radix-cache off, chunked-prefill-size 16384, conc 2/4/8, isl/osl 68k/350.
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NV CI is all good, ROCm pre-existing condition |
Kimi Linear builds its MLA layers with skip_rope=True, which leaves rotary_emb as None. Since #35770 resolve_attn_backend() unwraps HybridLinearAttnBackend, so those layers now reach TokenspeedMLABackend.prepare_prefill_qkv, which dereferenced layer.rotary_emb unconditionally and crashed every TP rank in prefill: AttributeError: 'NoneType' object has no attribute 'cos_sin_cache' Branch once in prepare_prefill_qkv on layer.rotary_emb is None. With no rotation, Q is a plain cast into the packed [nope | pe] layout, done with fp8_quantize on each slice into one FP8 buffer (the row kernel needs a power-of-2 width). K packs and V quantizes with mla_kv_pack_quantize_fp8, the fused kernel prefix chunks already use. The RoPE path and the _fused_rope_fp8_quantize signature are unchanged, and the KV-cache write still takes head 0 of the packed K, which is the unrotated k_pe. Fixes test_kimi_linear_dcp4, test_kimi_linear_dcp_dspark4 and test_unified_radix_cache_kl_dcp on extra-b-test-4-gpu-b200.
Co-authored-by: clintg6 <7388379+clintg6@users.noreply.github.com> Co-authored-by: Thomas Wang <thomawan@amd.com> Co-authored-by: HAI <hixiao@gmail.com> Co-authored-by: kk <43161300+kkHuang-amd@users.noreply.github.com>
…cache The test has been failing ~50% of scheduled extra-b B200 runs since 09/11 with avg_kl_div 0.010-0.013 vs the 0.01 threshold. sgl-project#35770 routed Kimi Linear prefill through the tokenspeed_mla FP8 prepare_prefill_qkv hook, which doubled the KL from 0.003-0.006. Switch to cutedsl_mla on the default bf16 KV cache like every other KL test; threshold unchanged.
Motivation
Kimi-K3 uses two attention representations during prefill at TP8 on MI355X:
dimensions 576/512.
Current Triton prefill leaves performance on the table for both shapes:
online softmax.
increasing register pressure.
equivalent opt-in path.
Changes
K3 prefill tuning
prefill kernels.
log2(e)into the attention scale and useexp2for unmodified K3logits.
Triton-3.7 fallback.
4×128 absorbed MLA kernel
Add a dedicated split-dimension kernel for cached-prefix K3 MLA:
The kernel maintains one online-softmax state and four independent FP32
value accumulators before concatenating the normalized 128-wide outputs.
Dispatch is restricted to:
supported descales;
score modifier, auxiliary tensor, or skipped stage.
Unsupported calls immediately use the existing generic kernel.
FP8 prefill
Add:
This is enabled by default. Set
SGLANG_TRITON_FP8_PREFILL_ATTN=0to disablenative FP8 prefill.
On exact K3 gfx950 shapes:
matching Aiter behavior.
the FP8 cached prefix.
FP8_MAXbefore FP8 P·V andthe accumulator contribution is divided by the same factor.
The default-on path achieved 98% GSM8K accuracy in model-level validation.
Performance
MI355X measurements used a device warmup and HIP-graph replay.
Against unmodified current main:
FP8 zero-prefix compared with the optimized BF16 path:
The default-on policy intentionally follows Aiter and enables native FP8 at
every length despite the small 8K crossover loss.
End-to-end serving
Throughput uplift is computed as the geometric mean of the per-concurrency
ratios at concurrency 2, 4, 8, and 16.
Kimi-K3 TP8, ISL/OSL 8192/1024:
Kimi-K3 TP8, ISL/OSL 68K/350:
The long-context gain is predominantly improved prefill/TTFT; median ITL is
effectively unchanged in both comparisons.
Numerics
relative L2 approximately
9.5e-5.relative L2 approximately
6.6e-5.relative L2 approximately 3.4-3.5%.
Additional long-context logits and workload validation remain recommended.
Platform scope
All specialized execution paths require gfx950 and exact K3 shapes.
On NVIDIA and other AMD architectures:
exp2and two-stage specializations are disabled;Validation
git diff --checkpassed.stage-b-test-1-gpu-small-amd-mi35xsuite.Recommended E2E matrix:
Files changed
CI States
Latest PR Test (Base): ✅ Run #33842442737
Latest PR Test (Extra): ❌ Run #33842442510
Latest PR Test (AMD ROCm 7.2): ⏳ Run #33842442551