qwen 3.8 rebase - #35758
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Co-authored-by: cherichy <cherichy@outlook.com> Co-authored-by: guangyunh-nv <guangyunh@nvidia.com> Co-authored-by: jiahanc <jiahanc@nvidia.com> Co-authored-by: jinyangyuan-nvidia <joyuan@nvidia.com> Co-authored-by: Cheng Hang <chang@nvidia.com> Co-authored-by: Yicheng Qiang <yqiang@nvidia.com> Co-authored-by: Sam Li <lsam@nvidia.com> Co-authored-by: Tom-Zheng <tizheng@nvidia.com> Co-authored-by: Yangmin Li <yangminl@nvidia.com> Co-authored-by: xiaoweiw-nv <xiaoweiw@nvidia.com> Co-authored-by: Zheng Li <lizheng.cs@zju.edu.cn> Co-authored-by: yizhang2077 <1109276519@qq.com> Co-authored-by: Qiaolin Yu <liin1211@outlook.com> Co-authored-by: Ke Bao <ispobaoke@gmail.com> Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com> Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com> Co-authored-by: Zijie Xia <zijie.xia@radixark.ai>
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August 20, 2026 22:07
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Co-authored-by: cherichy <cherichy@outlook.com> Co-authored-by: guangyunh-nv <guangyunh@nvidia.com> Co-authored-by: jiahanc <jiahanc@nvidia.com> Co-authored-by: jinyangyuan-nvidia <joyuan@nvidia.com> Co-authored-by: Cheng Hang <chang@nvidia.com> Co-authored-by: Yicheng Qiang <yqiang@nvidia.com> Co-authored-by: Sam Li <lsam@nvidia.com> Co-authored-by: Tom-Zheng <tizheng@nvidia.com> Co-authored-by: Yangmin Li <yangminl@nvidia.com> Co-authored-by: xiaoweiw-nv <xiaoweiw@nvidia.com> Co-authored-by: Zheng Li <lizheng.cs@zju.edu.cn> Co-authored-by: yizhang2077 <1109276519@qq.com> Co-authored-by: Ke Bao <ispobaoke@gmail.com> Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com> Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com> Co-authored-by: Zijie Xia <zijie.xia@radixark.ai> Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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Co-authored-by: cherichy <cherichy@outlook.com> Co-authored-by: guangyunh-nv <guangyunh@nvidia.com> Co-authored-by: jiahanc <jiahanc@nvidia.com> Co-authored-by: jinyangyuan-nvidia <joyuan@nvidia.com> Co-authored-by: Cheng Hang <chang@nvidia.com> Co-authored-by: Yicheng Qiang <yqiang@nvidia.com> Co-authored-by: Sam Li <lsam@nvidia.com> Co-authored-by: Tom-Zheng <tizheng@nvidia.com> Co-authored-by: Yangmin Li <yangminl@nvidia.com> Co-authored-by: xiaoweiw-nv <xiaoweiw@nvidia.com> Co-authored-by: Zheng Li <lizheng.cs@zju.edu.cn> Co-authored-by: yizhang2077 <1109276519@qq.com> Co-authored-by: Ke Bao <ispobaoke@gmail.com> Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com> Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com> Co-authored-by: Zijie Xia <zijie.xia@radixark.ai> Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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sgl-project#35758) Decode fusion: the projected QKVZ/BA pair stays packed and one Triton kernel unpacks it, applies the indexed causal Conv1D state update, and materializes mixed_qkv/z/b/a, replacing the split kernel plus a second conv launch. Eligibility-checked with an explicit fallback, env-gated (SGLANG_ENABLE_GDN_DECODE_FUSED_PROJ_CONV, default on; names kept upstream-verbatim for future syncs), with an opt-in live parity check (SGLANG_GDN_DECODE_FUSION_VERIFY_REAL_TENSORS) and per-layer hit logs. Env vars registered per the Envs convention. Ported test covers parity vs split+causal_conv1d_update, widths 2-4, dtypes, CUDA-graph replay, OOB-slot masking, and the fp8 fallback (5/5 on H20). Measured on H20 TP1, dense 27B: neutral-to-slightly-positive decode (bs8 TPOT 18.91 vs 19.04 ms; bs64 21.91 vs 22.02 ms); gsm8k 200q 0.965 vs 0.975 (within run noise). Caveat: the live parity check fires during CUDA graph capture because capture dummy batches alias mamba slots across rows (reference uses a private state copy); it is a debug-only mode and real batches have unique slots.
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SGLANG_FLASHINFER_MNNVL_CUTEDSL_AR_FUSION_MAX_INSTANCES had no valid setting. The registry keys workspaces by full signature and one model configuration exists per process, so the count is an invariant rather than a knob; it is now a hardcoded guard with the same fail-closed behavior at the same call site. The optional-argument form of get_flashinfer_mnnvl_cutedsl_ar_fusion() went with it: the no-argument lookup only had to disambiguate between several workspaces, and its sole caller always supplied all five. The arguments are now required. Added in #35758 alongside the gate env var and never released, so no deprecation alias.
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Removes machinery that no caller reaches, most of it inherited from #35758. Workspace module: - The registry (signature dataclass, dict, RLock, best-fit search) held at most one entry once the instance cap became an invariant; it collapses to a single module global. - destroy() was never called and _destroyed was therefore always False, so supports() carried a check that could not fire. - moe_finalize_all_reduce_rms_norm / all_reduce_residual_rms_norm took optional norm_output / residual_output that only the unit test supplied; production always let them allocate. Fusion core: - The service re-validated shapes, dtypes and contiguity on every eligible layer of every forward. The handoff builds its own views, and the workspace already refuses an M it cannot serve, so this was duplicated work on the hot path. - supports() also duplicated the workspace's range check, and is_prepared was subsumed by it (supports() is False before prepare()). Qwen3.5 final norm: - SGLANG_TRACE_QWEN35_FINAL_NORM and SGLANG_QWEN35_NATIVE_FINAL_NORM were bring-up scaffolding: print() plus torch.cuda.synchronize() around the norm, and a forward_native A/B switch. Both env vars are deleted; like the other two they shipped in #35758 and were never released.
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initial pr: #34585
Following work
Note that comparing with the day 0 image, this pr is not using flashinfer gdn prefill cp kernel.
CI States
Latest PR Test (Base): 🚫 Run #33213936462
Latest PR Test (Extra): ✅ Run #33230635480
Latest PR Test (AMD ROCm 7.2): 🚫 Run #33213936196