[AMD] [Not-Merge] Move getSMVersion to runtime.cuh and fix ROCm compile (dedup with get_cc_major) - #31141
[AMD] [Not-Merge] Move getSMVersion to runtime.cuh and fix ROCm compile (dedup with get_cc_major)#31141kangwangamd wants to merge 4 commits into
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getSMVersion() (added by sgl-project#30438) calls cudaDeviceGetAttribute with the CUDA-only cudaDevAttrComputeCapabilityMajor/Minor enums. These do not exist under HIP, and since utils.cuh is an inline header included by nearly every JIT translation unit, this breaks JIT compilation of all DeepSeek-V4 kernels on gfx950 (MI355X) -- 8/9 mi355x-disagg benchmarks red. SM/compute-capability version is a CUDA-only concept with no ROCm-JIT caller (SM120 gating is done in Python), so guard the whole function with #ifndef USE_ROCM, matching the other guarded blocks in this file. No CUDA-path change. Compile-verified (hipcc -DUSE_ROCM): stock fails on gfx950 and gfx942 with 'use of undeclared identifier cudaDevAttrComputeCapabilityMajor/ Minor'; guarded compiles clean on both.
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Code Review
This pull request introduces an #ifndef USE_ROCM preprocessor guard around the getSMVersion function in utils.cuh. This change prevents compilation failures on ROCm platforms (such as gfx950) where CUDA-specific compute-capability attributes are not supported. There are no review comments, so I have no feedback to provide.
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Actually sglang/python/sglang/jit_kernel/include/sgl_kernel/runtime.cuh Lines 1 to 86 in 440aebd get_cc_major. Could you please help fix that? Also, the guard might not be needed after #31141
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Thanks @DarkSharpness, that's a much cleaner approach —
Will push shortly and re-verify the gfx950 compile. |
Per @DarkSharpness: instead of guarding getSMVersion out of utils.cuh on ROCm, move it into runtime.cuh where the cuda*->hip* attribute shims already live, so it compiles on both CUDA and HIP with no USE_ROCM guard. Add the cudaDevAttrComputeCapabilityMinor->hip #define + get_cc_minor, and express getSMVersion as get_cc_major*10 + get_cc_minor to deduplicate the compute-capability queries. No JIT-tree caller, so no use-site change. Compile-verified on gfx950 (MI355X): the moved function compiles clean via the HIP attribute shims (function present, not guarded out).
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@DarkSharpness done — pushed the rework:
Compile-verified on gfx950 (MI355X, |
| } | ||
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| // Return the SM version (major * 10 + minor) for the given device | ||
| inline auto getSMVersion(int device_id) -> int { |
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I'd prefer get_sm_version.
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Done — renamed to |
…get_cc_major) Adopt the reviewed approach from #31141 (per @DarkSharpness): instead of guarding CUDA-only getSMVersion with #ifndef USE_ROCM in utils.cuh, move the compute-capability query into runtime.cuh where the cuda*->hip* attribute shims already live, so it compiles on both CUDA and HIP with no guard. Add the cudaDevAttrComputeCapabilityMinor->hip #define + get_cc_minor, and express get_sm_version(id) = get_cc_major(id) * 10 + get_cc_minor(id) to dedup the compute-capability queries. getSMVersion has no JIT-tree caller, so no use-site change; removes the guarded getSMVersion from utils.cuh. Co-authored-by: kangwangamd <kangwang@amd.com>
…get_cc_major) Adopt the reviewed approach from #31141 (per @DarkSharpness): move the CUDA-only compute-capability query out of utils.cuh into runtime.cuh where the cuda*->hip* attribute shims already live, so it compiles on both CUDA and HIP with no #ifndef USE_ROCM guard. Add the cudaDevAttrComputeCapabilityMinor->hip #define + get_cc_minor, and express get_sm_version(id) = get_cc_major(id) * 10 + get_cc_minor(id). No JIT-tree caller, so no use-site change. Co-authored-by: kangwangamd <kangwang@amd.com>
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Closing this out — it was always marked |
Motivation
getSMVersion()(added by #30438, "Delete CUTLASS FP8 blockwise… move SM120 to JIT + SwapAB") lives inpython/sglang/jit_kernel/include/sgl_kernel/utils.cuhand calls:cudaDevAttrComputeCapabilityMajor/Minorare CUDA-only enums (SM / compute-capability is an NVIDIA concept) and do not exist under HIP. Becauseutils.cuhis an inline header included transitively by nearly every JIT translation unit, this fails to compile in every gfx950 (MI355X) JIT TU:This breaks JIT compilation of all DeepSeek-V4 kernels on gfx950, turning 8/9 MI355X-disaggregation benchmarks red (regression since #30438 landed; last-passing
4cec9ef9d, first-failing merge7431f35fd).Modifications
Guard
getSMVersion()with#ifndef USE_ROCM, matching the other CUDA-only blocks already guarded in this same file.getSMVersionhas no ROCm-JIT caller — its only reference in the JIT tree is its own definition, and the SM120 arch-gating is done in Python (fp8_blockwise_gemm.py→is_sm120_supported()), so guarding the whole function out on ROCm is safe. No CUDA-path change.Validation
Compile-verified with
hipcc -DUSE_ROCM(compile-only; no GPU needed since this is a compile-time break):undeclared identifier cudaDevAttrComputeCapability*→ "2 errors compiling for gfx950"cc @b8zhong (author of #30438) @BBuf — please take a look. Also cc @AMD-yanfeiwang @kkHuang-amd for ROCm review.
CI States
Latest PR Test (Base): ✅ Run #29559518750
Latest PR Test (Extra): ❌ Run #29559518679