[NVIDIA] Allow modelopt_mixed quantization with flashinfer_cutedsl MoE runner - #30443
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ModelOpt MIXED_PRECISION checkpoints with NVFP4 MoE layers (e.g. nvidia/Qwen3.5-397B-A17B-NVFP4-V2) resolve to quantization=modelopt_mixed and dispatch FusedMoE layers to the same ModelOptNvFp4FusedMoEMethod (with an embedded ModelOptFp4Config) as modelopt_fp4, which flashinfer_cutedsl already supports. The server-args gate and the DeepEPMoE deprecate_flag check only listed modelopt_fp4; extend both so mixed checkpoints take the same path.
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Follow-up to sgl-project#30443. MIXED_PRECISION checkpoints whose routed-expert layers are plain NVFP4 (e.g. nvidia/Qwen3.5-397B-A17B-NVFP4-V2) behave like modelopt_fp4 for MoE activation handling, but three heuristics still keyed on the quantization string alone: the SGLANG_MOE_NVFP4_DISPATCH auto-enable for --moe-a2a-backend flashinfer, the FP4-quantize-before-allgather path for flashinfer_cutlass, and the Qwen3-MoE-family default runner selection on sm100. Record whether a mixed checkpoint's expert entries are all NVFP4 (ModelConfig.mixed_nvfp4_moe) and include that in the three conditions. W4A16_NVFP4 experts keep bf16 activations and stay excluded.
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Motivation
ModelOpt MIXED_PRECISION checkpoints with NVFP4 MoE layers — e.g. nvidia/Qwen3.5-397B-A17B-NVFP4-V2 (NVFP4 routed experts, FP8 attention/shared experts) — resolve to
quantization=modelopt_mixedand fail to launch with--moe-runner-backend flashinfer_cutedsl:This is an allowlist gap, not a kernel limitation:
modelopt_mixeddispatches NVFP4 MoE layers to the sameModelOptNvFp4FusedMoEMethod(with an embeddedModelOptFp4Config) asmodelopt_fp4, which the cutedsl runner already supports, and the adjacentflashinfer_cutlass/flashinfer_trtllmasserts already acceptmodelopt_mixed.The assert's other escape,
nvfp4_moe_meta(the "hybrid NVFP4 models" case), does not help here because it detects a different config format. Mixed-precision ModelOpt checkpoints come in two shapes (abridged):Checkpoints of the second shape resolve to
quantization=modelopt_mixedand currently have no way through the cutedsl gate.Modifications
modelopt_mixednow takes the same path asmodelopt_fp4in the two places that gate the cutedsl runner:python/sglang/srt/server_args.py: acceptmodelopt_mixedin theflashinfer_cutedslquantization assert.python/sglang/srt/layers/moe/ep_moe/layer.py: accept it in theDeepEPMoEdeprecate_flagcheck, so cutedsl +--moe-a2a-backend deepepuses the FusedMoE runner path instead of the legacyDeepEPMoEinitialization, which has no branch for the mixed config.Mixed checkpoints whose MoE layers are not NVFP4 still pass this arg-level gate and are rejected at load time by the per-layer quant method — same behavior as the existing cutlass allowlist. Follow-up (not included): the
SGLANG_MOE_NVFP4_DISPATCHauto-enable and the cutlass FP4-allgather heuristic still key onmodelopt_fp4only; mixed deployments can set the env var explicitly.Verification
All on GB200 (sm_100) with
nvidia/Qwen3.5-397B-A17B-NVFP4-V2(TP4,--quantization modelopt_mixed --mamba-ssm-dtype bfloat16 --trust-remote-code):quantization=modelopt_mixed runner=flashinfer_cutedsland cutedsl-specific handling applies (--disable-shared-experts-fusionauto-set).(moe_runner_backend=flashinfer_cutedsl, quant_method=ModelOptNvFp4FusedMoEMethod); deterministic greedy outputs are correct.--moe-a2a-backend deepep --deepep-mode low_latency+ cutedsl (exercises modification 2): serves correctly; greedy outputs identical to the TP4 run. Needed--cuda-graph-max-bs-decode 32to stay within DeepEP LL's dispatch-token bound — a pre-existing sizing constraint orthogonal to this PR.sglang.test.run_eval(temperature 0, max_tokens 16384), identical args except the runner:flashinfer_cutedsl(this PR)flashinfer_cutlass(control)Parity within noise (0.5 pp, 1 of 200 questions).
Checklist
CI States
Latest PR Test (Base): ⏳ Run #28918596123
Latest PR Test (Extra): ❌ Run #28918596045