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…on ROCm The DSA fused metadata-copy JIT kernel includes <cuda_runtime.h> unconditionally. The tvm-ffi JIT path compiles the .cuh directly with `hipcc -x hip` (no hipify pass), so on ROCm there is no cuda_runtime.h on the include path and compilation fails: fused_metadata_copy.cuh:38:10: fatal error: 'cuda_runtime.h' file not found This is reached on AMD whenever speculative_num_steps > 3, which selects the multi-backend fused copy path (dsa_backend.py) -- the single-backend path is already HIP-guarded via `_USE_FUSED_METADATA_COPY ... and not _is_hip`, but the multi path is not. Because cache_once does not memoize failed compiles, the build is retried on every CUDA-graph replay and the DSA spec-decode loop falls back step-by-step, collapsing decode throughput (~0.13 tok/s on gfx950). Guarding the include with `#ifndef USE_ROCM` lets the kernel compile and run on ROCm (the rest of the file is HIP-compatible: __grid_constant__ is shimmed and the launcher has a hipLaunchKernelGGL branch). Verified on gfx950 / ROCm 7.2.4: the multi kernel now compiles cleanly and a functional test confirms it copies all metadata fields correctly to all three destination backends. Signed-off-by: andyluo7 <andy.luo@amd.com>
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Code Review
This pull request introduces a conditional preprocessor check in fused_metadata_copy.cuh to exclude the <cuda_runtime.h> header when compiling for ROCm (USE_ROCM is defined). This improves compatibility with AMD GPU environments. There are no review comments, and I have no additional feedback to provide.
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Could a maintainer please add the Why this matters (end-to-end validation on MI350X / gfx950, ROCm 7.2.4)Without this guard, any EAGLE/MTP run with Because With this PR (and, separately, the gfx950 block-FP8 accuracy fix tracked in #28685), a full
This PR only addresses the throughput cliff (the compile failure); it is independent of the accuracy issue in #28685. Verified the kernel both compiles and produces correct copies on gfx950 (functional test vs a torch reference, all metadata fields, both |
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@andyluo7 Please fix conflict, thanks |
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Superseded by #29373 (merged 2026-06-27 by @HaiShaw), which landed the same |
Summary
The DSA fused metadata-copy JIT kernel (
python/sglang/jit_kernel/csrc/elementwise/fused_metadata_copy.cuh) includes<cuda_runtime.h>unconditionally. The tvm-ffi JIT path compiles the.cuhdirectly withhipcc -x hipwithout a hipify pass, so on ROCm there is nocuda_runtime.hon the include path and compilation fails:This kernel is reached on AMD whenever
speculative_num_steps > 3, which selects the multi-backend fused-copy path indsa_backend.py. The single-backend path is already HIP-guarded (_USE_FUSED_METADATA_COPY = ... and not _is_hip), but the multi path is not. And becausecache_once(jit_kernel/utils.py) only memoizes successful compiles, the failed build is retried on every CUDA-graph replay — the call site catches the error and falls back to the per-backend loop, but pays a full failedhipccinvocation per decode step, collapsing throughput to ~0.13 tok/s on gfx950.The fix guards just the include with
#ifndef USE_ROCM. The rest of the file is already HIP-compatible:__grid_constant__is shimmed ininclude/sgl_kernel/utils.cuh, andhost::LaunchKernelhas ahipLaunchKernelGGLbranch.Test plan
Verified on MI350X (gfx950) / ROCm 7.2.4:
_jit_fused_metadata_copy_multi_module(...)fails with thecuda_runtime.hfatal error above.has_real_page_table∈ {false, true} andhas_flashmla∈ {false, true}.int32tensors and compared against a torch reference —cache_seqlens,cu_seqlens_k[1:], page table (col < max_len),dsa_cache_seqlens,dsa_cu_seqlens_k[1:], andreal_page_tableall copy exactly to all three destination backends; index-0 and the page-table tail are correctly left untouched. PASS for bothhas_real_page_tablefalse and true.Note: this restores
num_steps > 3throughput on ROCm; it is independent of the gfx950 block-FP8 accuracy issue tracked in #28685.CI States
Latest PR Test (Base): ❌ Run #27849498701
Latest PR Test (Extra): ❌ Run #27849498600