feat: WIP NIXL transfer through CPU buffer for better performance with mixed TP sizes#18968
feat: WIP NIXL transfer through CPU buffer for better performance with mixed TP sizes#18968Aphoh wants to merge 5 commits into
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Summary of ChangesHello @Aphoh, I'm Gemini Code Assist1! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed! This pull request introduces a substantial performance enhancement for NIXL-based KV cache transfers, particularly critical for scenarios involving mixed Tensor Parallelism configurations. By integrating custom Triton kernels and a dedicated pinned CPU buffer allocator, the system can now efficiently move KV cache data between GPU and host memory. This change drastically reduces the overhead associated with numerous small NIXL transactions, replacing them with fewer, larger, and more optimized transfers, leading to a more scalable and performant disaggregated inference setup. Highlights
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Code Review
This pull request introduces a significant performance enhancement for NIXL transfers, especially in mixed tensor-parallelism scenarios, by implementing a new transfer path via a pinned CPU buffer. This is achieved through new Triton kernels for efficient gather/scatter operations and a shared pinned buffer pool. The changes are extensive, well-structured, and include comprehensive tests and benchmarks, which is great. The new logic for handling mixed TP sizes and batched transfers appears sound. My review focuses on the correctness of the new implementation, and I've identified a minor issue in memory size calculation that should be addressed.
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| # Allocate GPU staging buffer (fixed size, 256MB by default) | ||
| staging_size_bytes = int(DEFAULT_TRITON_STAGING_BUFFER_SIZE_MB * 1e6) |
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The calculation of staging_size_bytes uses a decimal prefix (1e6 for MB). For memory sizes, it's standard and more accurate to use binary prefixes (powers of 1024). Using 1e6 results in allocating ~5% less memory than specified. Please use 1024**2 for megabytes (MiB) to ensure correct memory allocation.
| staging_size_bytes = int(DEFAULT_TRITON_STAGING_BUFFER_SIZE_MB * 1e6) | |
| staging_size_bytes = int(DEFAULT_TRITON_STAGING_BUFFER_SIZE_MB * 1024**2) |
| pinned_size_bytes = int( | ||
| getattr(self._server_args, "nixl_cpu_buffer_size_gb", 16.0) * 1e9 | ||
| ) |
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The calculation of pinned_size_bytes uses a decimal prefix (1e9 for GB). For memory sizes, it's standard and more accurate to use binary prefixes (powers of 1024). Using 1e9 results in allocating ~7% less memory than specified. Please use 1024**3 for gigabytes (GiB) to ensure correct memory allocation.
| pinned_size_bytes = int( | |
| getattr(self._server_args, "nixl_cpu_buffer_size_gb", 16.0) * 1e9 | |
| ) | |
| pinned_size_bytes = int( | |
| getattr(self._server_args, "nixl_cpu_buffer_size_gb", 16.0) * 1024**3 | |
| ) |
| f"staging={self.triton_staging_buffer.nbytes / 1e6:.2f}MB (GPU), " | ||
| f"shared_pinned_pool={pinned_size_bytes / 1e9:.2f}GB (CPU)" |
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To be consistent with using binary prefixes for memory sizes (MiB/GiB), the logging should also use powers of 1024 for reporting. This avoids confusion between decimal (MB/GB) and binary (MiB/GiB) units and correctly reflects the allocated memory after applying the suggested changes for memory calculation.
| f"staging={self.triton_staging_buffer.nbytes / 1e6:.2f}MB (GPU), " | |
| f"shared_pinned_pool={pinned_size_bytes / 1e9:.2f}GB (CPU)" | |
| f"staging={self.triton_staging_buffer.nbytes / (1024**2):.2f}MiB (GPU), " | |
| f"shared_pinned_pool={pinned_size_bytes / (1024**3):.2f}GiB (CPU)" |
Aphoh
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Triton gather/scatter kernels + shared pinned buffer reduce NIXL descriptor count from O(tokens * layers) to O(1), achieving ~100% PCIe bandwidth.
Previously TransferStatus tracked KV notifications by pp_rank, but in mixed TP (prefill_tp > decode_tp) multiple prefill TP ranks share the same pp_rank (0 when PP=1). The decode expected N unique senders but only ever saw one unique key, causing a 5-minute waiting_timeout. Fix: track by peer_name (unique NIXL agent UUID per TP rank) so each prefill TP rank is counted as a distinct sender. This mirrors the approach in the dd-rebased-058 branch.
For prefill_tp > decode_tp: - dst_head_offset was using the global local_tp_rank, causing prefill ranks in the second decode bucket (e.g. ranks 2,3 for prefill_tp=4, decode_tp=2) to write beyond the end of the decode node's pinned buffer. Fix: use (local_tp_rank % prefill_ranks_per_decode) so the offset is always relative to the decode bucket. For prefill_tp < decode_tp (batched path): - head_start was using the absolute decode_tp_rank, so prefill rank 1 (with local heads 0..H/2) would be asked to send heads starting at H/2, H/4*3, etc. which are out of range. Fix: use (decode_tp_rank % decode_per_prefill) as the relative rank within the group of decode ranks served by this prefill rank. Also update the "Performance is NOT guaranteed" warning: - Suppress it when --nixl-use-cpu-buffer is set (which now correctly handles head redistribution); emit an info_once instead. - When cpu buffer is NOT used, keep the warning and add a suggestion to use --nixl-use-cpu-buffer. Add DEBUG logging for both mixed-TP paths to aid future diagnosis.
Replace blocking torch.cuda.synchronize() after each Triton gather kernel with a non-blocking CUDA event. NixlKVSender.poll() checks event.query() and posts the NIXL transfer only once the gather completes, keeping the model forward pass unblocked. Also removes the scatter sync on the decode side (stream ordering is sufficient) and drops the backwards-compat shim in TransferInfo.from_zmq.
Each chunk computed dst_offset using the chunk token count instead of total, causing chunk N to overwrite chunk N-1. Accumulate kv_indices across chunks and issue a single gather+NIXL write on is_last=True. Accuracy on GSM8K prefill_tp_larger (TP4->TP2): 86.5% -> 95.0% TODO: revisit multi-chunk handling more cleanly in the future
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Motivation
Currently NIXL performs transfers between mixed TP nodes by issuing a single nixl transaction per token, layer, head. This is incredibly inefficient and any reasonable load will grind a deployment to a halt on KV transfer.
Modifications
Introduced three main components
1. Triton kernels for copying KVs to host
These kernels transpose the layout from
k_buffer[layer]: [num_slots, num_heads, head_dim]to[num_heads, num_layers, 2, num_tokens, head_dim]which lets us slice out heads and do a single nixl transfer per head we need to send.In benchmarking these kernels easily hit 90% of host to device bw.
2. A Pinned CPU buffer allocator
This slot-based allocator helps reduce how much CPU buffer we need to allocate on the host.
Accuracy Tests
The three tested configurations were equal TP (2,2), prefill TP > decode TP (4,2), and prefill TP < decode TP (2,4), all on Qwen3-8B.
Benchmarking and Profiling
bench_serving Results (Qwen/Qwen3-8B, 320 prompts, in=256, out=128, H200)
(4,2) — Prefill TP=4, Decode TP=2
(2,4) — Prefill TP=2, Decode TP=4
Checklist
Review Process
/tag-run-ci-label,/rerun-failed-ci,/tag-and-rerun-ci