Skip to content

Add dsv3 router gemm benchmark on blackwell - #17707

Merged
Fridge003 merged 47 commits into
sgl-project:mainfrom
harrisonlimh:dsv3_router_gemm
Apr 4, 2026
Merged

Fridge003 merged 47 commits into
sgl-project:mainfrom
harrisonlimh:dsv3_router_gemm

Conversation

@harrisonlimh

@harrisonlimh harrisonlimh commented Jan 25, 2026

Copy link
Copy Markdown
Collaborator

Motivation

Modifications

  • Add accuracy and performance benchmark script to compare dsv3_router_gemm from sglang kernel and flashinfer

Accuracy Tests

Confirmed accuracy tests pass for m=[1...16], n=256, k=7168, tp=[1...8] with PDL=[False, True]

devuser@fd4e69449b8a:/sgl-workspace/sglang$ python /sgl-workspace/sglang/benchmark/kernels/deepseek/benchmark_deepgemm_dsv3_router_gemm_blackwell.py --tp-sizes 1 2 3 4 5 6 7 8 
Running correctness tests...
Shape m=1, n=256, k=7168:
Using launch_with_pdl=False for flashinfer
Flashinfer output: tensor([-17.9624,  43.4657, -15.9304, -63.4333, -69.3980], device='cuda:0')
SGLang output: tensor([-17.9624,  43.4657, -15.9304, -63.4333, -69.3980], device='cuda:0')
Correctness check:
  - Flashinfer vs SGLang: ✅
Shape m=2, n=256, k=7168:
Using launch_with_pdl=False for flashinfer
Flashinfer output: tensor([109.2808, -43.0782,  37.6395,  26.0075,  32.4039], device='cuda:0')
SGLang output: tensor([109.2808, -43.0782,  37.6395,  26.0075,  32.4039], device='cuda:0')
Correctness check:
  - Flashinfer vs SGLang: ✅
Shape m=3, n=256, k=7168:
Using launch_with_pdl=False for flashinfer
Flashinfer output: tensor([ 128.8076,  -22.1988,  -19.9927,   88.4693, -238.1407],
       device='cuda:0')
SGLang output: tensor([ 128.8076,  -22.1988,  -19.9927,   88.4693, -238.1407],
       device='cuda:0')
Correctness check:
  - Flashinfer vs SGLang: ✅
Shape m=4, n=256, k=7168:
Using launch_with_pdl=False for flashinfer
Flashinfer output: tensor([ -18.6437, -161.4112,   13.0358,  -41.9130,   87.1818],
       device='cuda:0')
SGLang output: tensor([ -18.6437, -161.4112,   13.0358,  -41.9130,   87.1818],
       device='cuda:0')
Correctness check:
  - Flashinfer vs SGLang: ✅
 ...

Benchmarking and Profiling

Benchmark result

Flashinfer kernel performed better on below configs:

 m   n    k  tp_size  launch_with_pdl
 6 256 7168        4             True
 6 256 7168        6             True
 6 256 7168        7             True
 6 256 7168        8             True
14 256 7168        1             True
14 256 7168        2             True
14 256 7168        3             True
14 256 7168        6             True

Flashinfer kernel performed equally as the existing kernel on below configs:

 m   n    k  tp_size  launch_with_pdl
 6 256 7168        1             True
 6 256 7168        2             True
 6 256 7168        3             True
 6 256 7168        5             True
 7 256 7168        7             True
14 256 7168        5             True

In all other scenarios, the existing kernel performed better.

Full result

  • $ python /sgl-workspace/sglang/benchmark/kernels/deepseek/benchmark_deepgemm_dsv3_router_gemm_blackwell.py --tp-sizes 1 2 3 4 5 6 7 8 --plot-friendly
image
  • $ python /sgl-workspace/sglang/benchmark/kernels/deepseek/benchmark_deepgemm_dsv3_router_gemm_blackwell.py --tp-sizes 1 2 3 4 5 6 7 8
...

fp8-gemm-performance-comparison-tp-1-2-3-4-5-6-7-8:
     m    n     k  tp_size  launch_with_pdl     SGLang  Flashinfer
0     1  256  7168        1            False  15.392000   19.487999
1     2  256  7168        1            False  15.424000   19.487999
2     3  256  7168        1            False  15.360000   19.487999
3     4  256  7168        1            False  15.424000   19.487999
4     5  256  7168        1            False  17.312000   21.439999
5     6  256  7168        1            False  17.503999   21.568000
6     7  256  7168        1            False  17.503999   21.568000
7     8  256  7168        1            False  17.503999   21.536000
8     9  256  7168        1            False  19.520000   23.584001
9    10  256  7168        1            False  19.520000   23.584001
10   11  256  7168        1            False  19.520000   23.584001
11   12  256  7168        1            False  19.487999   23.584001
12   13  256  7168        1            False  21.407999   25.504000
13   14  256  7168        1            False  21.568000   25.632000
14   15  256  7168        1            False  21.600001   25.664000
15   16  256  7168        1            False  21.536000   25.664000
16    1  256  7168        2            False  15.424000   19.487999
17    2  256  7168        2            False  15.424000   19.487999
18    3  256  7168        2            False  15.424000   19.487999
19    4  256  7168        2            False  15.424000   19.487999
20    5  256  7168        2            False  17.376000   21.407999
21    6  256  7168        2            False  17.503999   21.536000
22    7  256  7168        2            False  17.440001   21.536000
23    8  256  7168        2            False  17.440001   21.536000
24    9  256  7168        2            False  19.520000   23.584001
25   10  256  7168        2            False  19.520000   23.584001
26   11  256  7168        2            False  19.520000   23.584001
27   12  256  7168        2            False  19.487999   23.584001
28   13  256  7168        2            False  21.439999   25.536001
29   14  256  7168        2            False  21.568000   25.632000
30   15  256  7168        2            False  21.600001   25.664000
31   16  256  7168        2            False  21.600001   25.664000
32    1  256  7168        3            False  15.360000   19.487999
33    2  256  7168        3            False  15.424000   19.487999
34    3  256  7168        3            False  15.424000   19.487999
35    4  256  7168        3            False  15.392000   19.487999
36    5  256  7168        3            False  17.312000   21.439999
37    6  256  7168        3            False  17.503999   21.536000
38    7  256  7168        3            False  17.440001   21.568000
39    8  256  7168        3            False  17.440001   21.536000
40    9  256  7168        3            False  19.520000   23.584001
41   10  256  7168        3            False  19.520000   23.584001
42   11  256  7168        3            False  19.455999   23.584001
43   12  256  7168        3            False  19.487999   23.584001
44   13  256  7168        3            False  21.472000   25.504000
45   14  256  7168        3            False  21.568000   25.632000
46   15  256  7168        3            False  21.600001   25.632000
47   16  256  7168        3            False  21.600001   25.664000
48    1  256  7168        4            False  15.360000   19.487999
49    2  256  7168        4            False  15.360000   19.487999
50    3  256  7168        4            False  15.424000   19.487999
51    4  256  7168        4            False  15.456000   19.487999
52    5  256  7168        4            False  17.472001   21.439999
53    6  256  7168        4            False  17.503999   21.568000
54    7  256  7168        4            False  17.503999   21.568000
55    8  256  7168        4            False  17.472001   21.536000
56    9  256  7168        4            False  19.520000   23.584001
57   10  256  7168        4            False  19.520000   23.584001
58   11  256  7168        4            False  19.520000   23.584001
59   12  256  7168        4            False  19.520000   23.584001
60   13  256  7168        4            False  21.472000   25.536001
61   14  256  7168        4            False  21.568000   25.632000
62   15  256  7168        4            False  21.600001   25.664000
63   16  256  7168        4            False  21.600001   25.632000
64    1  256  7168        5            False  15.360000   19.487999
65    2  256  7168        5            False  15.424000   19.487999
66    3  256  7168        5            False  15.424000   19.487999
67    4  256  7168        5            False  15.456000   19.487999
68    5  256  7168        5            False  17.376000   21.407999
69    6  256  7168        5            False  17.440001   21.568000
70    7  256  7168        5            False  17.503999   21.536000
71    8  256  7168        5            False  17.503999   21.536000
72    9  256  7168        5            False  19.455999   23.584001
73   10  256  7168        5            False  19.455999   23.584001
74   11  256  7168        5            False  19.520000   23.584001
75   12  256  7168        5            False  19.520000   23.584001
76   13  256  7168        5            False  21.504000   25.504000
77   14  256  7168        5            False  21.568000   25.632000
78   15  256  7168        5            False  21.600001   25.632000
79   16  256  7168        5            False  21.536000   25.664000
80    1  256  7168        6            False  15.456000   19.487999
81    2  256  7168        6            False  15.424000   19.487999
82    3  256  7168        6            False  15.424000   19.487999
83    4  256  7168        6            False  15.360000   19.487999
84    5  256  7168        6            False  17.376000   21.439999
85    6  256  7168        6            False  17.503999   21.568000
86    7  256  7168        6            False  17.440001   21.568000
87    8  256  7168        6            False  17.503999   21.536000
88    9  256  7168        6            False  19.455999   23.584001
89   10  256  7168        6            False  19.520000   23.584001
90   11  256  7168        6            False  19.520000   23.584001
91   12  256  7168        6            False  19.520000   23.584001
92   13  256  7168        6            False  21.504000   25.504000
93   14  256  7168        6            False  21.568000   25.632000
94   15  256  7168        6            False  21.536000   25.632000
95   16  256  7168        6            False  21.536000   25.664000
96    1  256  7168        7            False  15.424000   19.487999
97    2  256  7168        7            False  15.360000   19.487999
98    3  256  7168        7            False  15.360000   19.487999
99    4  256  7168        7            False  15.424000   19.487999
100   5  256  7168        7            False  17.472001   21.439999
101   6  256  7168        7            False  17.503999   21.536000
102   7  256  7168        7            False  17.503999   21.568000
103   8  256  7168        7            False  17.503999   21.536000
104   9  256  7168        7            False  19.520000   23.584001
105  10  256  7168        7            False  19.455999   23.584001
106  11  256  7168        7            False  19.487999   23.584001
107  12  256  7168        7            False  19.520000   23.584001
108  13  256  7168        7            False  21.455999   25.504000
109  14  256  7168        7            False  21.600001   25.632000
110  15  256  7168        7            False  21.600001   25.632000
111  16  256  7168        7            False  21.600001   25.632000
112   1  256  7168        8            False  15.424000   19.487999
113   2  256  7168        8            False  15.360000   19.487999
114   3  256  7168        8            False  15.360000   19.487999
115   4  256  7168        8            False  15.392000   19.487999
116   5  256  7168        8            False  17.472001   21.439999
117   6  256  7168        8            False  17.503999   21.536000
118   7  256  7168        8            False  17.503999   21.536000
119   8  256  7168        8            False  17.440001   21.536000
120   9  256  7168        8            False  19.520000   23.584001
121  10  256  7168        8            False  19.520000   23.584001
122  11  256  7168        8            False  19.520000   23.584001
123  12  256  7168        8            False  19.520000   23.584001
124  13  256  7168        8            False  21.504000   25.536001
125  14  256  7168        8            False  21.568000   25.632000
126  15  256  7168        8            False  21.600001   25.664000
127  16  256  7168        8            False  21.568000   25.632000
128   1  256  7168        1             True  15.424000   17.440001
129   2  256  7168        1             True  15.360000   17.440001
130   3  256  7168        1             True  15.424000   17.440001
131   4  256  7168        1             True  15.424000   17.440001
132   5  256  7168        1             True  17.312000   17.440001
133   6  256  7168        1             True  17.440001   17.440001
134   7  256  7168        1             True  17.503999   17.535999
135   8  256  7168        1             True  17.440001   19.455999
136   9  256  7168        1             True  19.520000   21.536000
137  10  256  7168        1             True  19.455999   21.504000
138  11  256  7168        1             True  19.520000   21.536000
139  12  256  7168        1             True  19.520000   21.536000
140  13  256  7168        1             True  21.472000   21.536000
141  14  256  7168        1             True  21.600001   21.536000
142  15  256  7168        1             True  21.600001   23.488000
143  16  256  7168        1             True  21.600001   23.584001
144   1  256  7168        2             True  15.360000   17.440001
145   2  256  7168        2             True  15.360000   17.440001
146   3  256  7168        2             True  15.424000   17.440001
147   4  256  7168        2             True  15.392000   17.440001
148   5  256  7168        2             True  17.344000   17.440001
149   6  256  7168        2             True  17.440001   17.440001
150   7  256  7168        2             True  17.503999   17.535999
151   8  256  7168        2             True  17.503999   19.455999
152   9  256  7168        2             True  19.455999   21.536000
153  10  256  7168        2             True  19.520000   21.536000
154  11  256  7168        2             True  19.520000   21.536000
155  12  256  7168        2             True  19.520000   21.536000
156  13  256  7168        2             True  21.439999   21.536000
157  14  256  7168        2             True  21.568000   21.536000
158  15  256  7168        2             True  21.600001   23.488000
159  16  256  7168        2             True  21.536000   23.584001
160   1  256  7168        3             True  15.424000   17.440001
161   2  256  7168        3             True  15.424000   17.440001
162   3  256  7168        3             True  15.360000   17.440001
163   4  256  7168        3             True  15.424000   17.440001
164   5  256  7168        3             True  17.408000   17.440001
165   6  256  7168        3             True  17.440001   17.440001
166   7  256  7168        3             True  17.503999   17.600000
167   8  256  7168        3             True  17.503999   19.487999
168   9  256  7168        3             True  19.520000   21.536000
169  10  256  7168        3             True  19.455999   21.536000
170  11  256  7168        3             True  19.455999   21.536000
171  12  256  7168        3             True  19.487999   21.536000
172  13  256  7168        3             True  21.439999   21.536000
173  14  256  7168        3             True  21.568000   21.536000
174  15  256  7168        3             True  21.600001   23.520000
175  16  256  7168        3             True  21.600001   23.584001
176   1  256  7168        4             True  15.456000   17.440001
177   2  256  7168        4             True  15.424000   17.440001
178   3  256  7168        4             True  15.360000   17.440001
179   4  256  7168        4             True  15.424000   17.440001
180   5  256  7168        4             True  17.295999   17.440001
181   6  256  7168        4             True  17.503999   17.440001
182   7  256  7168        4             True  17.503999   17.535999
183   8  256  7168        4             True  17.503999   19.487999
184   9  256  7168        4             True  19.520000   21.536000
185  10  256  7168        4             True  19.520000   21.504000
186  11  256  7168        4             True  19.455999   21.568000
187  12  256  7168        4             True  19.520000   21.536000
188  13  256  7168        4             True  21.504000   21.536000
189  14  256  7168        4             True  21.536000   21.568000
190  15  256  7168        4             True  21.536000   23.488000
191  16  256  7168        4             True  21.536000   23.552001
192   1  256  7168        5             True  15.424000   17.440001
193   2  256  7168        5             True  15.424000   17.440001
194   3  256  7168        5             True  15.360000   17.440001
195   4  256  7168        5             True  15.440000   17.440001
196   5  256  7168        5             True  17.376000   17.440001
197   6  256  7168        5             True  17.440001   17.440001
198   7  256  7168        5             True  17.503999   17.535999
199   8  256  7168        5             True  17.440001   19.455999
200   9  256  7168        5             True  19.520000   21.504000
201  10  256  7168        5             True  19.455999   21.536000
202  11  256  7168        5             True  19.455999   21.536000
203  12  256  7168        5             True  19.520000   21.536000
204  13  256  7168        5             True  21.439999   21.504000
205  14  256  7168        5             True  21.568000   21.568000
206  15  256  7168        5             True  21.600001   23.456000
207  16  256  7168        5             True  21.600001   23.584001
208   1  256  7168        6             True  15.360000   17.408000
209   2  256  7168        6             True  15.424000   17.440001
210   3  256  7168        6             True  15.424000   17.440001
211   4  256  7168        6             True  15.456000   17.440001
212   5  256  7168        6             True  17.376000   17.440001
213   6  256  7168        6             True  17.503999   17.472001
214   7  256  7168        6             True  17.503999   17.535999
215   8  256  7168        6             True  17.503999   19.487999
216   9  256  7168        6             True  19.520000   21.536000
217  10  256  7168        6             True  19.520000   21.536000
218  11  256  7168        6             True  19.520000   21.568000
219  12  256  7168        6             True  19.520000   21.504000
220  13  256  7168        6             True  21.472000   21.504000
221  14  256  7168        6             True  21.568000   21.536000
222  15  256  7168        6             True  21.536000   23.488000
223  16  256  7168        6             True  21.600001   23.584001
224   1  256  7168        7             True  15.424000   17.440001
225   2  256  7168        7             True  15.424000   17.440001
226   3  256  7168        7             True  15.360000   17.440001
227   4  256  7168        7             True  15.424000   17.440001
228   5  256  7168        7             True  17.312000   17.440001
229   6  256  7168        7             True  17.503999   17.440001
230   7  256  7168        7             True  17.503999   17.503999
231   8  256  7168        7             True  17.440001   19.487999
232   9  256  7168        7             True  19.520000   21.504000
233  10  256  7168        7             True  19.520000   21.504000
234  11  256  7168        7             True  19.455999   21.536000
235  12  256  7168        7             True  19.520000   21.536000
236  13  256  7168        7             True  21.439999   21.536000
237  14  256  7168        7             True  21.504000   21.536000
238  15  256  7168        7             True  21.568000   23.488000
239  16  256  7168        7             True  21.600001   23.584001
240   1  256  7168        8             True  15.424000   17.440001
241   2  256  7168        8             True  15.392000   17.440001
242   3  256  7168        8             True  15.360000   17.440001
243   4  256  7168        8             True  15.424000   17.440001
244   5  256  7168        8             True  17.312000   17.440001
245   6  256  7168        8             True  17.472001   17.440001
246   7  256  7168        8             True  17.503999   17.535999
247   8  256  7168        8             True  17.503999   19.487999
248   9  256  7168        8             True  19.520000   21.536000
249  10  256  7168        8             True  19.520000   21.536000
250  11  256  7168        8             True  19.520000   21.536000
251  12  256  7168        8             True  19.520000   21.504000
252  13  256  7168        8             True  21.439999   21.536000
253  14  256  7168        8             True  21.504000   21.536000
254  15  256  7168        8             True  21.600001   23.456000
255  16  256  7168        8             True  21.600001   23.584001

Checklist

Review Process

  1. Ping Merge Oncalls to start the PR flow. See the PR Merge Process.
  2. Get approvals from CODEOWNERS and other reviewers.
  3. Trigger CI tests with comments or contact authorized users to do so.
    • /tag-run-ci-label, /rerun-failed-ci, /tag-and-rerun-ci
  4. After green CI and required approvals, ask Merge Oncalls to merge.

@gemini-code-assist

Copy link
Copy Markdown
Contributor

Summary of Changes

Hello @harrisonlimh, I'm Gemini Code Assist1! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed!

This pull request introduces a comprehensive benchmarking suite to evaluate the dsv3_router_gemm operation on Blackwell architecture. The primary objective is to compare the performance and numerical accuracy of the existing SGLang kernel with an alternative Flashinfer implementation, aiming to identify potential performance bottlenecks and optimization opportunities for this critical GEMM operation.

Highlights

  • New Benchmark Script: Introduces a new Python script for benchmarking the dsv3_router_gemm operation specifically on Blackwell GPUs.
  • Kernel Performance Comparison: Compares the performance and accuracy of the existing sglang kernel against the flashinfer implementation for dsv3_router_gemm.
  • Accuracy Validation: Confirms that both sglang and flashinfer kernels produce numerically accurate results across various m, n, k, and tensor parallelism (tp) configurations, including scenarios with and without launch_with_pdl.
  • Detailed Performance Insights: Provides comprehensive benchmark results, highlighting specific configurations where the flashinfer kernel demonstrates superior performance, matches the existing kernel, or performs less optimally.

🧠 New Feature in Public Preview: You can now enable Memory to help Gemini Code Assist learn from your team's feedback. This makes future code reviews more consistent and personalized to your project's style. Click here to enable Memory in your admin console.

Using Gemini Code Assist

The full guide for Gemini Code Assist can be found on our documentation page, here are some quick tips.

Invoking Gemini

You can request assistance from Gemini at any point by creating a comment using either /gemini <command> or @gemini-code-assist <command>. Below is a summary of the supported commands on the current page.

Feature Command Description
Code Review /gemini review Performs a code review for the current pull request in its current state.
Pull Request Summary /gemini summary Provides a summary of the current pull request in its current state.
Comment @gemini-code-assist Responds in comments when explicitly tagged, both in pull request comments and review comments.
Help /gemini help Displays a list of available commands.

Customization

To customize Gemini Code Assist for GitHub experience, repository maintainers can create a configuration file and/or provide a custom code review style guide (such as PEP-8 for Python) by creating and adding files to a .gemini/ folder in the base of the repository. Detailed instructions can be found here.

Limitations & Feedback

Gemini Code Assist may make mistakes. Please leave feedback on any instances where its feedback is incorrect or counter productive. You can react with 👍 and 👎 on @gemini-code-assist comments. If you're interested in giving your feedback about your experience with Gemini Code Assist for Github and other Google products, sign up here.

You can also get AI-powered code generation, chat, as well as code reviews directly in the IDE at no cost with the Gemini Code Assist IDE Extension.

Footnotes

  1. Review the Privacy Notices, Generative AI Prohibited Use Policy, Terms of Service, and learn how to configure Gemini Code Assist in GitHub here. Gemini can make mistakes, so double check it and use code with caution.

@gemini-code-assist gemini-code-assist Bot left a comment

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Code Review

This pull request adds a new benchmark script to compare the performance of dsv3_router_gemm from sglang and flashinfer on Blackwell architecture. The script includes both correctness checks and performance measurements.

My review focuses on improving the correctness, readability, and maintainability of the new benchmark script. I've identified a bug in the command-line argument parsing that makes a flag ineffective. I've also suggested several refactorings to clarify the logic, especially around handling benchmark timings, which is currently confusing and error-prone. Other suggestions include minor performance improvements and code simplification.

Comment on lines +116 to +140
if provider == "sglang":
ms, min_ms, max_ms = triton.testing.do_bench(
lambda: dsv3_router_gemm_sgl(
hidden_states.clone(memory_format=torch.contiguous_format),
router_weights.clone(memory_format=torch.contiguous_format),
),
quantiles=quantiles,
)
elif provider == "flashinfer":
ms, min_ms, max_ms = triton.testing.do_bench(
lambda: dsv3_router_gemm_flashinfer(
hidden_states.clone(memory_format=torch.contiguous_format),
router_weights.clone(memory_format=torch.contiguous_format),
launch_with_pdl,
),
quantiles=quantiles,
)

# Calculate TFLOPS
flops = 2 * m * n * k # multiply-adds
tflops = flops / (ms * 1e-3) / 1e12

# Print shape-specific results with TFLOPS
print(f"Time: {ms*1000:.2f} us, TFLOPS: {tflops:.2f}")
return ms, max_ms, min_ms

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

high

The handling of timing results from triton.testing.do_bench is confusing and error-prone due to variable naming and value swapping. do_bench returns (median, min, max). The current implementation swaps min and max values between functions, which makes the code hard to follow and maintain.

I suggest refactoring to use clearer variable names and a more direct data flow. This makes the code easier to understand and less prone to bugs. The suggested change also removes the redundant memory_format=torch.contiguous_format from .clone() calls, as the tensors are already contiguous.

You can refactor _benchmark as suggested. Then, in get_benchmark_plot_friendly and get_benchmark, the inner benchmark function should be updated to:

def benchmark(cfg_id, provider):
    m, n, k, tp_size, launch_with_pdl = all_configs[cfg_id]
    median_ms, min_ms, max_ms = _benchmark(m, n, k, tp_size, launch_with_pdl, provider)
    return median_ms * 1000, min_ms * 1000, max_ms * 1000
    if provider == "sglang":
        median_ms, min_ms, max_ms = triton.testing.do_bench(
            lambda: dsv3_router_gemm_sgl(
                hidden_states.clone(),
                router_weights.clone(),
            ),
            quantiles=quantiles,
        )
    elif provider == "flashinfer":
        median_ms, min_ms, max_ms = triton.testing.do_bench(
            lambda: dsv3_router_gemm_flashinfer(
                hidden_states.clone(),
                router_weights.clone(),
                launch_with_pdl,
            ),
            quantiles=quantiles,
        )

    # Calculate TFLOPS
    flops = 2 * m * n * k  # multiply-adds
    tflops = flops / (median_ms * 1e-3) / 1e12

    # Print shape-specific results with TFLOPS
    print(f"Time: {median_ms*1000:.2f} us, TFLOPS: {tflops:.2f}")
    return median_ms, min_ms, max_ms

Comment on lines +210 to +213
"--run-correctness",
action="store_true",
default=True,
help="Whether to run correctness test",

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

high

The argument --run-correctness is defined with action="store_true" and default=True. This combination makes the value of args.run_correctness always True, regardless of whether the flag is provided on the command line. This prevents disabling the correctness tests.

To make this flag work as intended (i.e., run correctness tests only when the flag is present), you should remove default=True. The default for action="store_true" is False.

        "--run-correctness",
        action="store_true",
        help="Whether to run correctness test",

import torch
import triton
from flashinfer.gemm.routergemm_dsv3 import mm_M1_16_K7168_N256
from sgl_kernel import dsv3_router_gemm as dsv3_router_gemm

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

medium

The alias dsv3_router_gemm is the same as the imported name. This is redundant and can be simplified for better code clarity.

Suggested change
from sgl_kernel import dsv3_router_gemm as dsv3_router_gemm
from sgl_kernel import dsv3_router_gemm

Comment on lines +28 to +33
output = torch.randn(
hidden_states.shape[0],
router_weights.shape[0],
device="cuda",
dtype=torch.float32,
).contiguous()

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

medium

The output tensor is initialized with random values using torch.randn, but its content is immediately overwritten by the mm_M1_16_K7168_N256 kernel. It's more efficient to just allocate the memory without initializing it by using torch.empty.

Suggested change
output = torch.randn(
hidden_states.shape[0],
router_weights.shape[0],
device="cuda",
dtype=torch.float32,
).contiguous()
output = torch.empty(
hidden_states.shape[0],
router_weights.shape[0],
device="cuda",
dtype=torch.float32,
).contiguous()

Comment on lines +69 to +75
mismatch_percent = 1.0 - match_ratio.item()
if mismatch_percent > 1 - percent:
print(
f"Mismatch percentage is {mismatch_percent:.4f} for rtol {rtol} "
f"(threshold: {1 - percent:.4f})"
)
return False

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

medium

The condition if mismatch_percent > 1 - percent: is redundant. If the code reaches this point, it means match_ratio < percent, which is equivalent to mismatch_percent > 1 - percent. This condition will always be true. You can simplify the logic by removing this if statement, making the code easier to understand.

    mismatch_percent = 1.0 - match_ratio.item()
    print(
        f"Mismatch percentage is {mismatch_percent:.4f} for rtol {rtol} "
        f"(threshold: {1 - percent:.4f})"
    )
    return False

Comment on lines +241 to +245
benchmark = (
get_benchmark_plot_friendly(args.tp_sizes)
if args.plot_friendly
else get_benchmark(args.tp_sizes)
)

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

medium

This line uses a ternary operator inside parentheses to select the benchmark function. While it works, a standard if/else block would be more readable and is generally preferred for this kind of logic.

    if args.plot_friendly:
        benchmark = get_benchmark_plot_friendly(args.tp_sizes)
    else:
        benchmark = get_benchmark(args.tp_sizes)

@harrisonlimh

Copy link
Copy Markdown
Collaborator Author

The result seems to suggest that the new flashinfer kernel only boosts the performance for m=6 and is limited to 0.365% gain.

As I am new to the area, I will wait for the team's review on the test set up before adding the usage of the kernel. cc: @Fridge003

Comment thread benchmark/kernels/deepseek/benchmark_deepgemm_dsv3_router_gemm_blackwell.py Outdated
@leejnau

leejnau commented Feb 3, 2026

Copy link
Copy Markdown
Collaborator

The result seems to suggest that the new flashinfer kernel only boosts the performance for m=6 and is limited to 0.365% gain.

As I am new to the area, I will wait for the team's review on the test set up before adding the usage of the kernel. cc: @Fridge003

@harrisonlimh Your findings are correct. This comes from the fact that both the sglang kernel and the current flashinfer kernel derive from the same TRTLLM kernel with some differences. So the performance being similar is expected. We plan to upgrade/fix the flashinfer kernel to have performance parity (or better) than the sglang kernel. Once there is an issue and/or work started on that we will let you know.

Thank you for your effort thus far on this.

@nv-yunzheq

nv-yunzheq commented Feb 3, 2026

Copy link
Copy Markdown

@harrisonlimh I think we should not compare the native implementation with launch_with_pdl set to False. To get it comparable with native integration, this parameter should be using the environment variable TRTLLM_ENABLE_PDL.
Could you update the performance result with this change? I'll investigate the rest of the regression.

@nv-yunzheq nv-yunzheq left a comment

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@harrisonlimh
Could you help fix the issues of tensor creation, pdl issue and rerun the benchmark? I think on kernel-level, two kernel should be identical, so no performance difference is expected.
Thanks!

launch_with_pdl: bool,
):
"""Flashinfer implementation of dsv3 router gemm"""
output = torch.randn(

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

As benchmark script, output should not be created with randn, as it introduce addtional overhead. We should use empty just like how SGLang function works.
Moreover, contiguous() is not needed, and it might intoduce additional overhead

Copy link
Copy Markdown
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Hi! Thank you for the feedback!

Please see below for follow ups!:

  • Made the suggested change and attached the result that compares PDL enabled and disabled results for flashinfer and sgl-kernel. The performance is on par as suggested.
  • The initial regression on flashinfer was caused by the use of radn and empty. Removing those alone confirmed that both kernels perform similarly.
  • Added slight refactoring to compare those kernels with both pdl on and off; launch_with_pdl param seems to take precedent over the env var for flashinfer, so used the env var for sgl-kernel and the launch_with_pdl for flashinfer kernel

@harrisonlimh

harrisonlimh commented Feb 4, 2026

Copy link
Copy Markdown
Collaborator Author

Flashinfer vs. SGLang kernel performance comparison
Performance is essentially on par between two kernels as explained by the team, especially when using PDL.

  1. With PDL
image
  1. Without PDL
image

Full benchmark data

  1. With PDL
fp8-gemm-performance-comparison-tp-1-2-3-4-5-6-7-8:
        m      n       k  tp_size     SGLang  Flashinfer
0     1.0  256.0  7168.0      1.0  13.344000   13.344000
1     2.0  256.0  7168.0      1.0  15.296000   15.296000
2     3.0  256.0  7168.0      1.0  15.392000   15.392000
3     4.0  256.0  7168.0      1.0  15.360000   15.360000
4     5.0  256.0  7168.0      1.0  15.360000   15.360000
5     6.0  256.0  7168.0      1.0  15.360000   15.360000
6     7.0  256.0  7168.0      1.0  15.360000   15.360000
7     8.0  256.0  7168.0      1.0  15.360000   15.392000
8     9.0  256.0  7168.0      1.0  17.408000   17.408000
9    10.0  256.0  7168.0      1.0  17.440001   17.440001
10   11.0  256.0  7168.0      1.0  19.392001   19.360000
11   12.0  256.0  7168.0      1.0  19.487999   19.455999
12   13.0  256.0  7168.0      1.0  19.455999   19.455999
13   14.0  256.0  7168.0      1.0  19.455999   19.487999
14   15.0  256.0  7168.0      1.0  19.455999   19.487999
15   16.0  256.0  7168.0      1.0  19.487999   19.487999
16    1.0  256.0  7168.0      2.0  13.376000   13.344000
17    2.0  256.0  7168.0      2.0  15.328000   15.328000
18    3.0  256.0  7168.0      2.0  15.392000   15.360000
19    4.0  256.0  7168.0      2.0  15.392000   15.360000
20    5.0  256.0  7168.0      2.0  15.360000   15.360000
21    6.0  256.0  7168.0      2.0  15.360000   15.360000
22    7.0  256.0  7168.0      2.0  15.360000   15.360000
23    8.0  256.0  7168.0      2.0  15.392000   15.392000
24    9.0  256.0  7168.0      2.0  17.408000   17.408000
25   10.0  256.0  7168.0      2.0  17.440001   17.440001
26   11.0  256.0  7168.0      2.0  19.392001   19.360000
27   12.0  256.0  7168.0      2.0  19.487999   19.487999
28   13.0  256.0  7168.0      2.0  19.455999   19.455999
29   14.0  256.0  7168.0      2.0  19.455999   19.455999
30   15.0  256.0  7168.0      2.0  19.455999   19.455999
31   16.0  256.0  7168.0      2.0  19.487999   19.455999
32    1.0  256.0  7168.0      3.0  13.344000   13.344000
33    2.0  256.0  7168.0      3.0  15.296000   15.328000
34    3.0  256.0  7168.0      3.0  15.360000   15.392000
35    4.0  256.0  7168.0      3.0  15.392000   15.360000
36    5.0  256.0  7168.0      3.0  15.360000   15.360000
37    6.0  256.0  7168.0      3.0  15.360000   15.360000
38    7.0  256.0  7168.0      3.0  15.360000   15.360000
39    8.0  256.0  7168.0      3.0  15.360000   15.360000
40    9.0  256.0  7168.0      3.0  17.408000   17.440001
41   10.0  256.0  7168.0      3.0  17.472001   17.440001
42   11.0  256.0  7168.0      3.0  19.424001   19.360000
43   12.0  256.0  7168.0      3.0  19.455999   19.487999
44   13.0  256.0  7168.0      3.0  19.487999   19.455999
45   14.0  256.0  7168.0      3.0  19.455999   19.455999
46   15.0  256.0  7168.0      3.0  19.455999   19.455999
47   16.0  256.0  7168.0      3.0  19.487999   19.487999
48    1.0  256.0  7168.0      4.0  13.344000   13.344000
49    2.0  256.0  7168.0      4.0  15.296000   15.328000
50    3.0  256.0  7168.0      4.0  15.392000   15.360000
51    4.0  256.0  7168.0      4.0  15.360000   15.360000
52    5.0  256.0  7168.0      4.0  15.360000   15.360000
53    6.0  256.0  7168.0      4.0  15.360000   15.360000
54    7.0  256.0  7168.0      4.0  15.360000   15.360000
55    8.0  256.0  7168.0      4.0  15.392000   15.392000
56    9.0  256.0  7168.0      4.0  17.408000   17.408000
57   10.0  256.0  7168.0      4.0  17.472001   17.440001
58   11.0  256.0  7168.0      4.0  19.392001   19.392001
59   12.0  256.0  7168.0      4.0  19.455999   19.487999
60   13.0  256.0  7168.0      4.0  19.455999   19.487999
61   14.0  256.0  7168.0      4.0  19.455999   19.487999
62   15.0  256.0  7168.0      4.0  19.455999   19.455999
63   16.0  256.0  7168.0      4.0  19.487999   19.487999
64    1.0  256.0  7168.0      5.0  13.344000   13.344000
65    2.0  256.0  7168.0      5.0  15.328000   15.296000
66    3.0  256.0  7168.0      5.0  15.360000   15.360000
67    4.0  256.0  7168.0      5.0  15.392000   15.360000
68    5.0  256.0  7168.0      5.0  15.360000   15.360000
69    6.0  256.0  7168.0      5.0  15.360000   15.360000
70    7.0  256.0  7168.0      5.0  15.392000   15.360000
71    8.0  256.0  7168.0      5.0  15.392000   15.392000
72    9.0  256.0  7168.0      5.0  17.408000   17.408000
73   10.0  256.0  7168.0      5.0  17.472001   17.440001
74   11.0  256.0  7168.0      5.0  19.392001   19.360000
75   12.0  256.0  7168.0      5.0  19.455999   19.455999
76   13.0  256.0  7168.0      5.0  19.487999   19.455999
77   14.0  256.0  7168.0      5.0  19.455999   19.455999
78   15.0  256.0  7168.0      5.0  19.455999   19.455999
79   16.0  256.0  7168.0      5.0  19.487999   19.487999
80    1.0  256.0  7168.0      6.0  13.344000   13.344000
81    2.0  256.0  7168.0      6.0  15.296000   15.296000
82    3.0  256.0  7168.0      6.0  15.392000   15.360000
83    4.0  256.0  7168.0      6.0  15.392000   15.360000
84    5.0  256.0  7168.0      6.0  15.360000   15.360000
85    6.0  256.0  7168.0      6.0  15.360000   15.360000
86    7.0  256.0  7168.0      6.0  15.360000   15.360000
87    8.0  256.0  7168.0      6.0  15.392000   15.360000
88    9.0  256.0  7168.0      6.0  17.408000   17.408000
89   10.0  256.0  7168.0      6.0  17.472001   17.408000
90   11.0  256.0  7168.0      6.0  19.392001   19.392001
91   12.0  256.0  7168.0      6.0  19.455999   19.487999
92   13.0  256.0  7168.0      6.0  19.455999   19.455999
93   14.0  256.0  7168.0      6.0  19.455999   19.487999
94   15.0  256.0  7168.0      6.0  19.455999   19.455999
95   16.0  256.0  7168.0      6.0  19.487999   19.487999
96    1.0  256.0  7168.0      7.0  13.344000   13.344000
97    2.0  256.0  7168.0      7.0  15.328000   15.296000
98    3.0  256.0  7168.0      7.0  15.360000   15.392000
99    4.0  256.0  7168.0      7.0  15.360000   15.360000
100   5.0  256.0  7168.0      7.0  15.360000   15.360000
101   6.0  256.0  7168.0      7.0  15.360000   15.360000
102   7.0  256.0  7168.0      7.0  15.360000   15.360000
103   8.0  256.0  7168.0      7.0  15.360000   15.392000
104   9.0  256.0  7168.0      7.0  17.408000   17.408000
105  10.0  256.0  7168.0      7.0  17.472001   17.440001
106  11.0  256.0  7168.0      7.0  19.392001   19.360000
107  12.0  256.0  7168.0      7.0  19.455999   19.455999
108  13.0  256.0  7168.0      7.0  19.455999   19.455999
109  14.0  256.0  7168.0      7.0  19.455999   19.455999
110  15.0  256.0  7168.0      7.0  19.487999   19.487999
111  16.0  256.0  7168.0      7.0  19.487999   19.455999
112   1.0  256.0  7168.0      8.0  13.344000   13.344000
113   2.0  256.0  7168.0      8.0  15.296000   15.296000
114   3.0  256.0  7168.0      8.0  15.360000   15.360000
115   4.0  256.0  7168.0      8.0  15.360000   15.392000
116   5.0  256.0  7168.0      8.0  15.360000   15.360000
117   6.0  256.0  7168.0      8.0  15.360000   15.360000
118   7.0  256.0  7168.0      8.0  15.360000   15.360000
119   8.0  256.0  7168.0      8.0  15.392000   15.392000
120   9.0  256.0  7168.0      8.0  17.408000   17.408000
121  10.0  256.0  7168.0      8.0  17.440001   17.440001
122  11.0  256.0  7168.0      8.0  19.360000   19.360000
123  12.0  256.0  7168.0      8.0  19.487999   19.455999
124  13.0  256.0  7168.0      8.0  19.455999   19.487999
125  14.0  256.0  7168.0      8.0  19.455999   19.455999
126  15.0  256.0  7168.0      8.0  19.455999   19.487999
127  16.0  256.0  7168.0      8.0  19.455999   19.487999
  1. Without PDL
fp8-gemm-performance-comparison-tp-1-2-3-4-5-6-7-8:
        m      n       k  tp_size     SGLang  Flashinfer
0     1.0  256.0  7168.0      1.0  17.184000   15.552000
1     2.0  256.0  7168.0      1.0  15.552000   16.416000
2     3.0  256.0  7168.0      1.0  15.552000   15.520000
3     4.0  256.0  7168.0      1.0  15.616000   15.552000
4     5.0  256.0  7168.0      1.0  17.440001   17.440001
5     6.0  256.0  7168.0      1.0  17.568000   17.632000
6     7.0  256.0  7168.0      1.0  17.568000   17.535999
7     8.0  256.0  7168.0      1.0  17.600000   17.600000
8     9.0  256.0  7168.0      1.0  19.680001   19.680001
9    10.0  256.0  7168.0      1.0  19.680001   19.680001
10   11.0  256.0  7168.0      1.0  19.616000   19.680001
11   12.0  256.0  7168.0      1.0  21.472000   21.439999
12   13.0  256.0  7168.0      1.0  21.536000   21.536000
13   14.0  256.0  7168.0      1.0  21.695999   21.663999
14   15.0  256.0  7168.0      1.0  21.663999   21.632001
15   16.0  256.0  7168.0      1.0  21.632001   21.728000
16    1.0  256.0  7168.0      2.0  15.712000   15.584000
17    2.0  256.0  7168.0      2.0  15.552000   15.616000
18    3.0  256.0  7168.0      2.0  15.616000   15.664000
19    4.0  256.0  7168.0      2.0  15.680000   15.904000
20    5.0  256.0  7168.0      2.0  17.535999   17.440001
21    6.0  256.0  7168.0      2.0  17.600000   17.632000
22    7.0  256.0  7168.0      2.0  17.568000   17.664000
23    8.0  256.0  7168.0      2.0  17.535999   17.632000
24    9.0  256.0  7168.0      2.0  19.648001   19.711999
25   10.0  256.0  7168.0      2.0  19.616000   19.584000
26   11.0  256.0  7168.0      2.0  19.648001   19.680001
27   12.0  256.0  7168.0      2.0  21.472000   21.536000
28   13.0  256.0  7168.0      2.0  21.504000   21.472000
29   14.0  256.0  7168.0      2.0  21.728000   21.695999
30   15.0  256.0  7168.0      2.0  21.760000   21.695999
31   16.0  256.0  7168.0      2.0  21.663999   21.695999
32    1.0  256.0  7168.0      3.0  15.552000   15.520000
33    2.0  256.0  7168.0      3.0  15.584000   15.552000
34    3.0  256.0  7168.0      3.0  15.584000   15.648000
35    4.0  256.0  7168.0      3.0  15.552000   17.247999
36    5.0  256.0  7168.0      3.0  17.472001   17.376000
37    6.0  256.0  7168.0      3.0  17.568000   17.632000
38    7.0  256.0  7168.0      3.0  17.600000   17.632000
39    8.0  256.0  7168.0      3.0  17.600000   17.600000
40    9.0  256.0  7168.0      3.0  19.680001   19.648001
41   10.0  256.0  7168.0      3.0  19.680001   19.680001
42   11.0  256.0  7168.0      3.0  19.680001   19.711999
43   12.0  256.0  7168.0      3.0  21.472000   21.407999
44   13.0  256.0  7168.0      3.0  21.536000   21.504000
45   14.0  256.0  7168.0      3.0  21.695999   21.663999
46   15.0  256.0  7168.0      3.0  21.695999   21.695999
47   16.0  256.0  7168.0      3.0  21.695999   21.632001
48    1.0  256.0  7168.0      4.0  17.216001   15.552000
49    2.0  256.0  7168.0      4.0  15.616000   15.584000
50    3.0  256.0  7168.0      4.0  15.584000   15.584000
51    4.0  256.0  7168.0      4.0  17.279999   15.584000
52    5.0  256.0  7168.0      4.0  17.472001   17.440001
53    6.0  256.0  7168.0      4.0  17.632000   17.632000
54    7.0  256.0  7168.0      4.0  17.600000   17.696001
55    8.0  256.0  7168.0      4.0  17.535999   17.568000
56    9.0  256.0  7168.0      4.0  19.648001   19.648001
57   10.0  256.0  7168.0      4.0  19.648001   19.680001
58   11.0  256.0  7168.0      4.0  21.183999   19.616000
59   12.0  256.0  7168.0      4.0  21.472000   21.439999
60   13.0  256.0  7168.0      4.0  21.536000   21.439999
61   14.0  256.0  7168.0      4.0  21.712000   21.695999
62   15.0  256.0  7168.0      4.0  21.695999   21.695999
63   16.0  256.0  7168.0      4.0  21.695999   21.663999
64    1.0  256.0  7168.0      5.0  15.520000   15.584000
65    2.0  256.0  7168.0      5.0  15.520000   15.648000
66    3.0  256.0  7168.0      5.0  15.584000   15.680000
67    4.0  256.0  7168.0      5.0  15.680000   15.584000
68    5.0  256.0  7168.0      5.0  17.440001   17.408000
69    6.0  256.0  7168.0      5.0  17.568000   17.632000
70    7.0  256.0  7168.0      5.0  17.600000   17.535999
71    8.0  256.0  7168.0      5.0  17.600000   17.600000
72    9.0  256.0  7168.0      5.0  19.711999   19.680001
73   10.0  256.0  7168.0      5.0  19.680001   19.616000
74   11.0  256.0  7168.0      5.0  19.648001   19.648001
75   12.0  256.0  7168.0      5.0  21.439999   21.376001
76   13.0  256.0  7168.0      5.0  21.472000   21.536000
77   14.0  256.0  7168.0      5.0  21.728000   21.695999
78   15.0  256.0  7168.0      5.0  21.695999   21.663999
79   16.0  256.0  7168.0      5.0  21.632001   21.663999
80    1.0  256.0  7168.0      6.0  15.520000   15.616000
81    2.0  256.0  7168.0      6.0  15.648000   15.584000
82    3.0  256.0  7168.0      6.0  15.680000   15.584000
83    4.0  256.0  7168.0      6.0  17.247999   17.247999
84    5.0  256.0  7168.0      6.0  17.503999   17.408000
85    6.0  256.0  7168.0      6.0  17.632000   17.664000
86    7.0  256.0  7168.0      6.0  17.632000   17.600000
87    8.0  256.0  7168.0      6.0  17.568000   17.632000
88    9.0  256.0  7168.0      6.0  19.616000   19.711999
89   10.0  256.0  7168.0      6.0  19.648001   19.648001
90   11.0  256.0  7168.0      6.0  19.648001   19.584000
91   12.0  256.0  7168.0      6.0  21.439999   21.439999
92   13.0  256.0  7168.0      6.0  21.536000   21.504000
93   14.0  256.0  7168.0      6.0  21.663999   21.728000
94   15.0  256.0  7168.0      6.0  21.760000   21.663999
95   16.0  256.0  7168.0      6.0  21.695999   21.728000
96    1.0  256.0  7168.0      7.0  15.584000   15.552000
97    2.0  256.0  7168.0      7.0  15.584000   15.616000
98    3.0  256.0  7168.0      7.0  15.584000   15.520000
99    4.0  256.0  7168.0      7.0  15.648000   16.720000
100   5.0  256.0  7168.0      7.0  17.503999   17.344000
101   6.0  256.0  7168.0      7.0  17.568000   17.632000
102   7.0  256.0  7168.0      7.0  17.535999   17.632000
103   8.0  256.0  7168.0      7.0  17.632000   17.535999
104   9.0  256.0  7168.0      7.0  19.648001   19.648001
105  10.0  256.0  7168.0      7.0  19.648001   19.616000
106  11.0  256.0  7168.0      7.0  19.680001   19.680001
107  12.0  256.0  7168.0      7.0  21.439999   21.407999
108  13.0  256.0  7168.0      7.0  21.536000   21.536000
109  14.0  256.0  7168.0      7.0  21.695999   21.728000
110  15.0  256.0  7168.0      7.0  21.663999   21.632001
111  16.0  256.0  7168.0      7.0  21.728000   21.695999
112   1.0  256.0  7168.0      8.0  15.648000   15.584000
113   2.0  256.0  7168.0      8.0  15.552000   15.616000
114   3.0  256.0  7168.0      8.0  15.552000   15.616000
115   4.0  256.0  7168.0      8.0  15.744001   15.632000
116   5.0  256.0  7168.0      8.0  17.535999   17.440001
117   6.0  256.0  7168.0      8.0  17.568000   17.632000
118   7.0  256.0  7168.0      8.0  17.632000   17.568000
119   8.0  256.0  7168.0      8.0  17.632000   17.535999
120   9.0  256.0  7168.0      8.0  19.648001   19.680001
121  10.0  256.0  7168.0      8.0  19.680001   19.616000
122  11.0  256.0  7168.0      8.0  19.648001   19.648001
123  12.0  256.0  7168.0      8.0  21.504000   21.439999
124  13.0  256.0  7168.0      8.0  21.439999   21.472000
125  14.0  256.0  7168.0      8.0  21.695999   21.728000
126  15.0  256.0  7168.0      8.0  21.728000   21.632001
127  16.0  256.0  7168.0      8.0  21.728000   21.728000

@leejnau

leejnau commented Feb 4, 2026

Copy link
Copy Markdown
Collaborator

@harrisonlimh I discussed with @nv-yunzheq and based on your current findings with PDL enabled showing performance parity, it is safe to proceed with integrating the flashinfer dsv3 router gemm.

@Fridge003
Fridge003 merged commit 9fa12d6 into sgl-project:main Apr 4, 2026
241 of 300 checks passed
@b8zhong

b8zhong commented Apr 4, 2026

Copy link
Copy Markdown
Collaborator

Hi @leejnau @harrisonlimh , this PR breaks SM103, it seems CC 103 was not added to FI (it should be compat anyway...)


[2026-04-04 19:33:24 TP0] Scheduler hit an exception: Traceback (most recent call last):
  File "/sgl-workspace/sglang/python/sglang/srt/managers/scheduler.py", line 3600, in run_scheduler_process
    scheduler = Scheduler(
                ^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/managers/scheduler.py", line 385, in __init__
    self.init_model_worker()
  File "/sgl-workspace/sglang/python/sglang/srt/managers/scheduler.py", line 632, in init_model_worker
    self.init_tp_model_worker()
  File "/sgl-workspace/sglang/python/sglang/srt/managers/scheduler.py", line 600, in init_tp_model_worker
    self.tp_worker = TpModelWorker(**worker_kwargs)
                     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/managers/tp_worker.py", line 261, in __init__
    self._init_model_runner()
  File "/sgl-workspace/sglang/python/sglang/srt/managers/tp_worker.py", line 344, in _init_model_runner
    self._model_runner = ModelRunner(
                         ^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/model_executor/model_runner.py", line 427, in __init__
    self.initialize(pre_model_load_memory)
  File "/sgl-workspace/sglang/python/sglang/srt/model_executor/model_runner.py", line 655, in initialize
    self.init_device_graphs()
  File "/sgl-workspace/sglang/python/sglang/srt/model_executor/model_runner.py", line 2455, in init_device_graphs
    self.graph_runner = graph_runners[self.device](self)
                        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/model_executor/cuda_graph_runner.py", line 653, in __init__
    self.capture()
  File "/sgl-workspace/sglang/python/sglang/srt/model_executor/cuda_graph_runner.py", line 809, in capture
    _capture_one_stream()
  File "/sgl-workspace/sglang/python/sglang/srt/model_executor/cuda_graph_runner.py", line 796, in _capture_one_stream
    ) = self.capture_one_batch_size(bs, forward, stream_idx)
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/model_executor/cuda_graph_runner.py", line 1024, in capture_one_batch_size
    run_once()
  File "/sgl-workspace/sglang/python/sglang/srt/model_executor/cuda_graph_runner.py", line 1011, in run_once
    logits_output_or_pp_proxy_tensors = forward(
                                        ^^^^^^^^
  File "/usr/local/lib/python3.12/dist-packages/torch/utils/_contextlib.py", line 120, in decorate_context
    return func(*args, **kwargs)
           ^^^^^^^^^^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/models/deepseek_v2.py", line 2207, in forward
    hidden_states = self.model(
                    ^^^^^^^^^^^
  File "/usr/local/lib/python3.12/dist-packages/torch/nn/modules/module.py", line 1775, in _wrapped_call_impl
    return self._call_impl(*args, **kwargs)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/local/lib/python3.12/dist-packages/torch/nn/modules/module.py", line 1786, in _call_impl
    return forward_call(*args, **kwargs)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/models/deepseek_v2.py", line 2018, in forward
    hidden_states, residual = layer(
                              ^^^^^^
  File "/usr/local/lib/python3.12/dist-packages/torch/nn/modules/module.py", line 1775, in _wrapped_call_impl
    return self._call_impl(*args, **kwargs)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/local/lib/python3.12/dist-packages/torch/nn/modules/module.py", line 1786, in _call_impl
    return forward_call(*args, **kwargs)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/models/deepseek_v2.py", line 1708, in forward
    hidden_states = self.mlp(
                    ^^^^^^^^^
  File "/usr/local/lib/python3.12/dist-packages/torch/nn/modules/module.py", line 1775, in _wrapped_call_impl
    return self._call_impl(*args, **kwargs)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/local/lib/python3.12/dist-packages/torch/nn/modules/module.py", line 1786, in _call_impl
    return forward_call(*args, **kwargs)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/models/deepseek_v2.py", line 561, in forward
    return self.forward_normal_dual_stream(
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/models/deepseek_v2.py", line 597, in forward_normal_dual_stream
    router_logits = self.gate(hidden_states, gemm_output_zero_allocator)
                    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/local/lib/python3.12/dist-packages/torch/nn/modules/module.py", line 1775, in _wrapped_call_impl
    return self._call_impl(*args, **kwargs)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/local/lib/python3.12/dist-packages/torch/nn/modules/module.py", line 1786, in _call_impl
    return forward_call(*args, **kwargs)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/models/deepseek_v2.py", line 338, in forward
    flashinfer_dsv3_router_gemm(logits, hidden_states, self.weight)
  File "/usr/local/lib/python3.12/dist-packages/torch/_ops.py", line 1255, in __call__
    return self._op(*args, **kwargs)
           ^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/sgl-workspace/sglang/python/sglang/srt/models/deepseek_v2.py", line 2284, in flashinfer_dsv3_router_gemm
    _raw_dsv3_router_gemm(
  File "/usr/local/lib/python3.12/dist-packages/flashinfer/utils.py", line 1229, in wrapper
    raise BackendSupportedError(
flashinfer.utils.BackendSupportedError: mm_M1_16_K7168_N256 does not support compute capability 103

Could either of you help upd: https://github.com/flashinfer-ai/flashinfer/blob/19329d838236803c59c8f571d42910b1c0c2a18e/flashinfer/gemm/routergemm.py#L180 to add 103 to supported CC? Thanks~

@harrisonlimh

Copy link
Copy Markdown
Collaborator Author

Hi @b8zhong, thank you for the heads up on this!

Would a simple allowlisting be sufficient to enable the kernal for SM 103?

@nvpohanh

nvpohanh commented Apr 6, 2026

Copy link
Copy Markdown
Collaborator

@leejnau Could you check if this is a FlashInfer bug/issue? That kernel should work for both SM100 and SM103

@Fridge003

Copy link
Copy Markdown
Collaborator

@b8zhong This issue is bypassed with #22134

JustinTong0323 pushed a commit to JustinTong0323/sglang that referenced this pull request Apr 7, 2026
bkryu added a commit to flashinfer-ai/flashinfer that referenced this pull request Apr 8, 2026
…2991)

<!-- .github/pull_request_template.md -->

add SM 103 support for mm_M1_16_K7168_N256. cc: @b8zhong, @Fridge003,
@leejnau

<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->

## 🔍 Related Issues
* sgl-project/sglang#17707

<!-- Link any related issues here -->

## 🚀 Pull Request Checklist

Thank you for contributing to FlashInfer! Before we review your pull
request, please make sure the following items are complete.

### ✅ Pre-commit Checks

- [ ] I have installed `pre-commit` by running `pip install pre-commit`
(or used your preferred method).
- [ ] I have installed the hooks with `pre-commit install`.
- [ ] I have run the hooks manually with `pre-commit run --all-files`
and fixed any reported issues.

> If you are unsure about how to set up `pre-commit`, see [the
pre-commit documentation](https://pre-commit.com/).

## 🧪 Tests

- [ ] Tests have been added or updated as needed.
- [ ] All tests are passing (`unittest`, etc.).

## Reviewer Notes

<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.
-->


<!-- This is an auto-generated comment: release notes by coderabbit.ai
-->
## Summary by CodeRabbit

* **Chores**
* Broadened GPU architecture support so optimized matrix-multiplication
routines also target an additional modern compute capability.
* **Tests**
* Updated test gating so positive and negative tests for the optimized
routine run on the newly supported compute capability as well.
<!-- end of auto-generated comment: release notes by coderabbit.ai -->

---------

Co-authored-by: Brian K. Ryu <bryu@nvidia.com>
caitengwei pushed a commit to caitengwei/sglang that referenced this pull request Jun 1, 2026
Chronostasys pushed a commit to MindLab-Research/sglang that referenced this pull request Aug 24, 2026
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

deepseek run-ci CI: run the baseline test suite on this PR

Projects

None yet

Development

Successfully merging this pull request may close these issues.

6 participants