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[SM100] Support per-expert normalization for MegaMoE - #104

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Fridge003 merged 2 commits into
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codex/muse-spark-mega-moe-patch
Oct 16, 2026
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Fridge003 merged 2 commits into
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codex/muse-spark-mega-moe-patch

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@Fridge003 Fridge003 commented Oct 16, 2026 •

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MegaMoE gains optional post-expert RMS normalization before combining routed expert outputs, including an optional FP32 gain and weight-first normalization. This ports the MegaMoE changes from the Muse Spark DeepGEMM patch onto current dev.

  • Add normalization support to the BF16 and FP8/FP4 paths, with workspace accumulation for fused partial sums.
  • Include the NVFP4 scale-inverse lookup table, store-tile tuning and DG_MEGA_MOE_TILES override, normalization test mode, DG_SKIP_LEGACY option, and recipe fix.
  • Adapt the original TVM-FFI changes to the current TORCH_LIBRARY wrappers and schemas, retaining the SiTU template parameters introduced after the patch's cbe1727 base.

Validation:

  • Reconstructed the original patch on cbe1727 and checked the port for retained changes.
  • git diff --check and Python syntax checks pass.
  • Both operator schemas parse, and Python/C++ argument counts and ordering agree.
  • The two adapted C++ bindings pass clang++ -std=c++20 -fsyntax-only against local PyTorch headers and the current MegaMoE API declarations. This checks the host bindings, not CUDA compilation.
  • Rebuilt the wheel and JIT kernels at b1c6fb0 on 4 x GB300 (SM103, driver 580.178.04), PyTorch 2.13.0+cu130, CUDA 13.0, GCC 13.3, in an isolated environment.
  • All 18 targeted GPU validation runs passed: post-expert norm on 1/4 ranks for BF16, FP8xFP4 and FP8xFP8; 4-rank PyTorch normalization/combine reference checks including NVFP4 and FP8 combine; zero/masked inputs, signed routing weights, epsilon, gain ordering, repeated calls and CUDA Graph replays; BF16 hidden=8192; NVFP4 alphas; BF16/NVFP4 TRT-LLM layouts; SiTU; and balanced/uneven/idle-rank global-token cases. The maximum normalization relative L2 error across 28 reference cases was 0.168%.
  • The NVFP4 scale-inverse lookup matched the original reciprocal implementation bitwise on 1,048,576 float2 samples and all 256 table entries.
  • Single-GPU memcheck and synccheck passed for BF16, FP8xFP4 and NVFP4, each with 0 reported errors. Unfiltered synccheck hit an internal nvjet launch error in the PyTorch reference matmul, also reproduced without DeepGEMM. The final synccheck runs use the repository's existing --kernel-name-exclude kns=nvjet setting; all DeepGEMM kernels remain instrumented.
  • This was targeted kernel correctness validation, not a full release-suite or performance benchmark run.

Import docker/muse_spark/deep_gemm.patch from sgl-project/sglang at ba5b73d08096066cd35f02a95d469be91c21219b. Adapt its bindings to TORCH_LIBRARY and preserve current SiTU template parameters.
@Fridge003 Fridge003 changed the title [SM100] Port Muse Spark MegaMoE normalization and tuning patch [SM100] Support per-expert normalization for MegaMoE Oct 16, 2026
@Fridge003
Fridge003 merged commit b296ce3 into dev Oct 16, 2026
@Fridge003
Fridge003 deleted the codex/muse-spark-mega-moe-patch branch October 16, 2026 06:57
zcnrex added a commit that referenced this pull request Oct 16, 2026
…-ai#471) into dev

Two-parent merge of upstream 1fc9c66 (deepseek-ai#441, deepseek-ai#462, deepseek-ai#471) into sgl dev
b296ce3, keeping the SGL wheel, the TORCH_LIBRARY binding and the
downstream kernels.

- Mega MoE: upstream locality-domain scheduling, 4D weight TMA, L1/L2 store
  blocks and the TMEM prefetch epilogue, with NVFP4/MXFP4, TRT-LLM weights,
  alphas, SiTU and FP8 combine carried over. TRT weights stay unlocalized.
- GEMM epilogue classes threaded through every dispatch; SM90/SM120 assert
  that no custom epilogue is set. SM120 kernels drop the head-split epilogue
  parameter, as upstream did for SM90.
- Attention takes upstream's API as-is: no clean_logits/logits_dtype, no
  legacy fp8_mqa_logits/fp8_paged_mqa_logits, no fp8_gemm_nt_skip_head_mid.
  The SM120 MQA kernels that only served the old API are removed.
- Mega gate is sqrtsoftplus-only; bf16_mega_gate defaults to it and
  get_bf16_mega_gate_config is gone.
- TORCH_LIBRARY binding: epilogue classes (Identity, Alpha,
  FP8CastWithClamp, BF16StochasticRounding) cross as
  (kind, scalar, sfd, count) into every GEMM/einsum op; shutdown and the
  locality-domain ops are registered; MLOPart reaches Python through ctypes
  callbacks installed by deep_gemm/locality_domain.py, which re-raises the
  callback's exception from the allocating call.
- sgl_deep_gemm tests pick up upstream's test changes and the new
  test_locality_domain.py.
- Dev's per-expert post-norm (#104) sits on upstream's restructured epilogue
  and combine. Its store block of 48 at block_m 192 becomes the L1 store
  block, upstream's FP8xFP4 L1/L2 blocks at 240 are kept, and
  DG_MEGA_MOE_TILES sets both L1 and L2.
- deep_jit stays at dev's 3732a3b, a descendant of upstream's 2efdab4.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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