Elfloader: NVIDIA Jetson Orin support

elfloader-tool/src/arch-arm/armv/armv8-a/64/smp.c

@@ -35,6 +35,12 @@ void core_entry(uint64_t sp)
 
 int is_core_up(int i)
 {
+    /* Secondary core may be booted with caches disabled,
+     * this value might be written in memory, invalidate our
+     * copy and get a new one. */
+    asm volatile("dc ivac, %0\n\t"
+                 "dmb nsh\n\t"
+                 :: "r"(&core_up[i]));
     return core_up[i] == i;
 }
 

elfloader-tool/src/arch-arm/drivers/smp-psci.c

@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: GPL-2.0-only
  */
+#include <autoconf.h>
 #include <elfloader_common.h>
 #include <devices_gen.h>
 #include <drivers/common.h>
@@ -24,7 +25,13 @@ static int smp_psci_cpu_on(UNUSED struct elfloader_device *dev,
     }
     secondary_data.entry = entry;
     secondary_data.stack = stack;
-    dmb();
+#if defined(CONFIG_ARCH_AARCH64)
+    /* If the secondary core caches are off, need to make sure that the info
+     * is clean to the physical memory so that the sedcondary cores can read it.
+     */
+    asm volatile("dc cvac, %0" :: "r"(&secondary_data));
+    dsb();
+#endif
     int ret = psci_cpu_on(cpu->cpu_id, (unsigned long)&secondary_startup, 0);
     if (ret != PSCI_SUCCESS) {
         printf("Failed to bring up core 0x%x with error %d\n", cpu->cpu_id, ret);

elfloader-tool/src/arch-arm/smp_boot.c

@@ -34,7 +34,11 @@ void non_boot_main(void)
 #endif
     /* Spin until the first CPU has finished initialisation. */
     while (!non_boot_lock) {
-#ifndef CONFIG_ARCH_AARCH64
+#ifdef CONFIG_ARCH_AARCH64
+        /* The compiler may optimize this loop away, add a dsb()
+         * to force a reload. */
+        dsb();
+#else
         cpu_idle();
 #endif
     }
@@ -124,7 +128,13 @@ WEAK void init_cpus(void)
             abort();
         }
 
-        while (!is_core_up(num_cpus));
+        while (!is_core_up(num_cpus)) {
+#if defined(CONFIG_ARCH_AARCH64)
+            /* The compiler may optimize this loop away, add a dsb()
+             * to force a reload. */
+            dsb();
+#endif
+        }
         printf("Core %d is up with logic id %d\n", elfloader_cpus[i].cpu_id, num_cpus);
         num_cpus++;
     }
@@ -141,6 +151,13 @@ void smp_boot(void)
     arm_disable_dcaches();
 #endif
     init_cpus();
+#if defined(CONFIG_ARCH_AARCH64)
+    dsb();
+    non_boot_lock = 1;
+    /* Secondary CPUs may still run with MMU & caches off. Force the update to be visible. */
+    asm volatile("dc civac, %0\n\t" :: "r"(&non_boot_lock) : "memory");;
+#else
     non_boot_lock = 1;
+#endif
 }
 #endif /* CONFIG_MAX_NUM_NODES */