On a risc-v build, the second argument received from OpenSBI seems to be getting clobbered

[mpolitzer]

The value of bootloader_dtb in main, arch-riscv/boot.c:290 does not correspond to the arg1 from OpenSBI.
The patch below seems to fix the problem.

NOTE: tested with -DElfloaderIncludeDtb=OFF

diff --git a/elfloader-tool/src/arch-riscv/crt0.S b/elfloader-tool/src/arch-riscv/crt0.S
index 40ab09e..28a218c 100644
--- a/elfloader-tool/src/arch-riscv/crt0.S
+++ b/elfloader-tool/src/arch-riscv/crt0.S
@@ -32,6 +32,7 @@ _start:
 
 /* a0 should have hart id, store it in s0 so as not to clobber from HSM calls */
   mv s0, a0
+  mv s2, a1
 
 #ifdef CONFIG_IMAGE_BINARY
 /* Clear the BSS before we get to do anything more specific */
@@ -83,6 +84,7 @@ _start1:
 
   la sp, (elfloader_stack_alloc + BIT(12))
 
+  mv a1, s2
   la s0, main
   jr s0

[axel-h]

Thanks, can you make a pull request with this patch?

[mpolitzer]

sure, please have a look: #103