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elfloader: arm: do not hard-code values
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Use existing defines to make the code more descriptive. For this
move some defines out of the assembler-only file.

This is a preparation patch for upcoming patches.

No functional change.

Signed-off-by: Matthias Rosenfelder <[email protected]>
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@mro-github-12345
mro-github-12345 authored and Andy Bui committed Feb 25, 2024
1 parent 65b49ae commit fa81fff
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Showing 3 changed files with 71 additions and 61 deletions.
65 changes: 65 additions & 0 deletions elfloader-tool/include/arch-arm/64/mode/aarch64.h
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@@ -0,0 +1,65 @@
/*
* Copyright 2023, NIO GmbH
*
* SPDX-License-Identifier: GPL-2.0-only
*/
#pragma once

/* This file contains useful defines for assembly and C code. */

#define PSR_F_BIT 0x00000040
#define PSR_I_BIT 0x00000080
#define PSR_A_BIT 0x00000100
#define PSR_D_BIT 0x00000200

#define PSR_MODE_EL0t 0x00000000
#define PSR_MODE_EL1t 0x00000004
#define PSR_MODE_EL1h 0x00000005
#define PSR_MODE_EL2t 0x00000008
#define PSR_MODE_EL2h 0x00000009
#define PSR_MODE_SVC_32 0x00000013

#define TCR_T0SZ(x) ((64 - (x)))
#define TCR_T1SZ(x) ((64 - (x)) << 16)
#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))

#define TCR_IRGN0_WBWC (1 << 8)
#define TCR_IRGN_NC ((0 << 8) | (0 << 24))
#define TCR_IRGN_WBWA ((1 << 8) | (1 << 24))
#define TCR_IRGN_WT ((2 << 8) | (2 << 24))
#define TCR_IRGN_WBnWA ((3 << 8) | (3 << 24))
#define TCR_IRGN_MASK ((3 << 8) | (3 << 24))

#define TCR_ORGN0_WBWC (1 << 10)
#define TCR_ORGN_NC ((0 << 10) | (0 << 26))
#define TCR_ORGN_WBWA ((1 << 10) | (1 << 26))
#define TCR_ORGN_WT ((2 << 10) | (2 << 26))
#define TCR_ORGN_WBnWA ((3 << 10) | (3 << 26))
#define TCR_ORGN_MASK ((3 << 10) | (3 << 26))

#define TCR_SH0_ISH (3 << 12)
#define TCR_SHARED ((3 << 12) | (3 << 28))

#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG1_4K (2 << 30)
#define TCR_TG1_64K (3 << 30)

#define TCR_PS_4G (0 << 16)
#define TCR_PS_64G (1 << 16)
#define TCR_PS_1T (2 << 16)
#define TCR_PS_4T (3 << 16)
#define TCR_PS_16T (4 << 16)
#define TCR_PS_256T (5 << 16)

/* bits are reserved as 1 */
#define TCR_EL2_RES1 ((1 << 23) | (1 << 31))
#define TCR_ASID16 (1 << 36)

#define MT_DEVICE_nGnRnE 0
#define MT_DEVICE_nGnRE 1
#define MT_DEVICE_GRE 2
#define MT_NORMAL_NC 3
#define MT_NORMAL 4
#define MT_NORMAL_WT 5
#define MAIR(_attr, _mt) ((_attr) << ((_mt) * 8))
58 changes: 1 addition & 57 deletions elfloader-tool/include/arch-arm/64/mode/assembler.h
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Expand Up @@ -9,63 +9,7 @@
/* This file contains useful macros for assembly code. */

#ifdef __ASSEMBLER__

#define PSR_F_BIT 0x00000040
#define PSR_I_BIT 0x00000080
#define PSR_A_BIT 0x00000100
#define PSR_D_BIT 0x00000200

#define PSR_MODE_EL0t 0x00000000
#define PSR_MODE_EL1t 0x00000004
#define PSR_MODE_EL1h 0x00000005
#define PSR_MODE_EL2t 0x00000008
#define PSR_MODE_EL2h 0x00000009
#define PSR_MODE_SVC_32 0x00000013

#define TCR_T0SZ(x) ((64 - (x)))
#define TCR_T1SZ(x) ((64 - (x)) << 16)
#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))

#define TCR_IRGN0_WBWC (1 << 8)
#define TCR_IRGN_NC ((0 << 8) | (0 << 24))
#define TCR_IRGN_WBWA ((1 << 8) | (1 << 24))
#define TCR_IRGN_WT ((2 << 8) | (2 << 24))
#define TCR_IRGN_WBnWA ((3 << 8) | (3 << 24))
#define TCR_IRGN_MASK ((3 << 8) | (3 << 24))

#define TCR_ORGN0_WBWC (1 << 10)
#define TCR_ORGN_NC ((0 << 10) | (0 << 26))
#define TCR_ORGN_WBWA ((1 << 10) | (1 << 26))
#define TCR_ORGN_WT ((2 << 10) | (2 << 26))
#define TCR_ORGN_WBnWA ((3 << 10) | (3 << 26))
#define TCR_ORGN_MASK ((3 << 10) | (3 << 26))

#define TCR_SH0_ISH (3 << 12)
#define TCR_SHARED ((3 << 12) | (3 << 28))

#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG1_4K (2 << 30)
#define TCR_TG1_64K (3 << 30)

#define TCR_PS_4G (0 << 16)
#define TCR_PS_64G (1 << 16)
#define TCR_PS_1T (2 << 16)
#define TCR_PS_4T (3 << 16)
#define TCR_PS_16T (4 << 16)
#define TCR_PS_256T (5 << 16)

/* bits are reserved as 1 */
#define TCR_EL2_RES1 ((1 << 23) | (1 << 31))
#define TCR_ASID16 (1 << 36)

#define MT_DEVICE_nGnRnE 0
#define MT_DEVICE_nGnRE 1
#define MT_DEVICE_GRE 2
#define MT_NORMAL_NC 3
#define MT_NORMAL 4
#define MT_NORMAL_WT 5
#define MAIR(_attr, _mt) ((_attr) << ((_mt) * 8))
#include <mode/aarch64.h>

.macro disable_mmu sctlr tmp
__disable_mmu \sctlr, \tmp
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9 changes: 5 additions & 4 deletions elfloader-tool/src/arch-arm/64/mmu.c
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Expand Up @@ -11,6 +11,7 @@
#include <mode/structures.h>
#include <printf.h>
#include <abort.h>
#include <mode/aarch64.h>
#include <armv/machine.h>

/*
Expand All @@ -31,7 +32,7 @@ void init_boot_vspace(struct image_info *kernel_info)
for (i = 0; i < BIT(PUD_BITS); i++) {
_boot_pud_down[i] = (i << ARM_1GB_BLOCK_BITS)
| BIT(10) /* access flag */
| (0 << 2) /* strongly ordered memory */
| (MT_DEVICE_nGnRnE << 2) /* strongly ordered memory */
| BIT(0); /* 1G block */
}

Expand All @@ -52,7 +53,7 @@ void init_boot_vspace(struct image_info *kernel_info)
#if CONFIG_MAX_NUM_NODES > 1
| (3 << 8) /* make sure the shareability is the same as the kernel's */
#endif
| (4 << 2) /* MT_NORMAL memory */
| (MT_NORMAL << 2) /* MT_NORMAL memory */
| BIT(0); /* 2M block */
first_paddr += BIT(ARM_2MB_BLOCK_BITS);
}
Expand All @@ -74,7 +75,7 @@ void init_hyp_boot_vspace(struct image_info *kernel_info)
for (i = 0; i < BIT(PUD_BITS); i++) {
_boot_pud_down[i] = (i << ARM_1GB_BLOCK_BITS)
| BIT(10) /* access flag */
| (0 << 2) /* strongly ordered memory */
| (MT_DEVICE_nGnRnE << 2) /* strongly ordered memory */
| BIT(0); /* 1G block */
}

Expand All @@ -91,7 +92,7 @@ void init_hyp_boot_vspace(struct image_info *kernel_info)
#if CONFIG_MAX_NUM_NODES > 1
| (3 << 8)
#endif
| (4 << 2) /* MT_NORMAL memory */
| (MT_NORMAL << 2) /* MT_NORMAL memory */
| BIT(0); /* 2M block */
}
}

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