Skip to content

improve RISC-V multi core boot #175

improve RISC-V multi core boot

improve RISC-V multi core boot #175

Triggered via pull request October 24, 2023 14:02
@axel-haxel-h
synchronize #132
Status Skipped
Total duration 7s
Artifacts
This run and associated checks have been archived and are scheduled for deletion. Learn more about checks retention

sel4test-hw.yml

on: pull_request_target
Matrix: HW Build
Matrix: HW Run
Fit to window
Zoom out
Zoom in