Jiahan CS 6120 Final Project Blog#423

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jiahanxie353 wants to merge 19 commits intosampsyo:2023fafrom jiahanxie353:2023fa

+173

Commits on Dec 11, 2023

first draft of the report for the final project
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Commits on Jan 7, 2024

fix some typo and wording
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correct the real unique part of riscv v extension; emphasize the real power of vl agnostic over traditional simd is when it comes loops
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qualify that it's the ABI imposes the fact that v0, v8, v16 can be used, not the rvv spec
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reword vector 'basic block' to simply just vector 'element'; recalculate vlmax
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change VF to M for LLVM scalable vectors
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clarify that lowerCall is not implemented yet
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rephrase about G_ADD legality and 'basic block'
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PseudoVADD_VV_MF8 is RISCV specific
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rephrase the instruction selection implementation part
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Commits on Jan 8, 2024