GitHub - rzhao01/ECE532_Project: Connect 5 with FPGA Accelerated AI using HLS

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Name		Name	Last commit message	Last commit date
Latest commit History 44 Commits
hls/board_counts		hls/board_counts
system		system
temp		temp
LICENSE		LICENSE
Makefile		Makefile
README		README
ai.c		ai.c
ai.h		ai.h
board.c		board.c
board.h		board.h
common.h		common.h
experiment.c		experiment.c
graphics.c		graphics.c
graphics.h		graphics.h
main.c		main.c

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Course Project for ECE532

Connect 5 with an AI that runs in hardware on an Atlys board with a Xillinx FPGA. Vivado HLS will be used to help generated the hardware.

Board is represented in bitboard format. Each row is an integer, so board is int[BOARD_ROWS]. Can have at most 32 columns. Unused columns are wasted.

Requires libsdl1.2-dev and libsdl-gfx1.2-dev