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What is Tiny Tapeout?

TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

Wokwi Projects

Edit the info.yaml and change the wokwi_id to the ID of your Wokwi project. You can find the ID in the URL of your project, it's the big number after wokwi.com/projects/.

The GitHub action will automatically fetch the digital netlist from Wokwi and build the ASIC files.

Verilog Projects

Edit the info.yaml and uncomment the source_files and top_module properties, and change the value of language to "Verilog". Add your Verilog files to the src folder, and list them in the source_files property.

The GitHub action will automatically build the ASIC files using OpenLane.

Enable GitHub actions to build the results page

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  • Verilog 50.3%
  • SystemVerilog 44.8%
  • Tcl 4.9%