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Workarounds for all/any mask reductions on x86, armv7, and aarch64 #425

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Merged
alexcrichton merged 15 commits into from
May 4, 2018
Merged

Workarounds for all/any mask reductions on x86, armv7, and aarch64 #425

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1d4668f
Work arounds for LLVM6 code-gen bugs in all/any reductions
gnzlbg Apr 11, 2018
f99000b
test avx on all x86 targets
gnzlbg Apr 13, 2018
81641d6
disable assert_instr on avx test
gnzlbg Apr 27, 2018
985893e
enable all appropriate features
gnzlbg Apr 27, 2018
2d6cc25
disable assert_instr on x86+avx
gnzlbg May 4, 2018
a6bd57c
the fn_must_use is stable
gnzlbg May 4, 2018
4462afb
fix nbody example on armv7
gnzlbg May 4, 2018
bd8e0e8
fixup
gnzlbg May 4, 2018
17466e9
fixup
gnzlbg May 4, 2018
8819741
enable 64-bit wide mask MMX optimizations on x86_64 only
gnzlbg May 4, 2018
68f7719
remove coresimd dependency on cfg_if
gnzlbg May 4, 2018
4ee0c5a
allow wasm to fail
gnzlbg May 4, 2018
fec0a3a
use an env variable to disable assert_instr tests
gnzlbg May 4, 2018
c589b1c
disable m32x2 mask MMX optimization on macos
gnzlbg May 4, 2018
a1390be
move cfg_if to coresimd/macros.rs
gnzlbg May 4, 2018
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10 changes: 10 additions & 0 deletions ci/run.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -35,3 +35,13 @@ cargo_test() {

cargo_test
cargo_test "--release"

# Test x86 targets compiled with AVX.
case ${TARGET} in
x86*)
RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"
cargo_test "--release"

@alexcrichton alexcrichton Apr 13, 2018

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This'll somehow need to disable all the assert_instr tests as well as anything beneath avx is likely to generate different instructions with avx enabled

;;
*)
;;
esac
26 changes: 2 additions & 24 deletions coresimd/ppsv/api/masks_reductions.rs
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Expand Up @@ -5,37 +5,15 @@ macro_rules! impl_mask_reductions {
($id:ident) => {
impl $id {
/// Are `all` vector lanes `true`?
#[cfg(not(target_arch = "aarch64"))]
#[inline]
pub fn all(self) -> bool {
use coresimd::simd_llvm::simd_reduce_all;
unsafe { simd_reduce_all(self) }
unsafe { super::codegen::masks_reductions::All::all(self) }
}
/// Are `all` vector lanes `true`?
#[cfg(target_arch = "aarch64")]
#[inline]
pub fn all(self) -> bool {
// FIXME: Broken on AArch64
// https://bugs.llvm.org/show_bug.cgi?id=36796
self.and()
}

/// Is `any` vector lanes `true`?
#[cfg(not(target_arch = "aarch64"))]
#[inline]
pub fn any(self) -> bool {
use coresimd::simd_llvm::simd_reduce_any;
unsafe { simd_reduce_any(self) }
unsafe { super::codegen::masks_reductions::Any::any(self) }
}
/// Is `any` vector lanes `true`?
#[cfg(target_arch = "aarch64")]
#[inline]
pub fn any(self) -> bool {
// FIXME: Broken on AArch64
// https://bugs.llvm.org/show_bug.cgi?id=36796
self.or()
}

/// Are `all` vector lanes `false`?
#[inline]
pub fn none(self) -> bool {
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