Skip to content

test: update riscv32e-registers.rs for LLVM 24 MC diagnostic changes #159607

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
rust-bors merged 1 commit into from
Jul 22, 2026
Merged

test: update riscv32e-registers.rs for LLVM 24 MC diagnostic changes #159607

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
32 changes: 16 additions & 16 deletions .../riscv/riscv32e-registers.riscv32e.stderr → ...riscv32e-registers.riscv32e_llvm23.stderr
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:43:11
--> $DIR/riscv32e-registers.rs:57:11
|
LL | asm!("li x16, 0");
| ^^^^^^^^^
Expand All @@ -11,7 +11,7 @@ LL | li x16, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:46:11
--> $DIR/riscv32e-registers.rs:61:11
|
LL | asm!("li x17, 0");
| ^^^^^^^^^
Expand All @@ -23,7 +23,7 @@ LL | li x17, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:49:11
--> $DIR/riscv32e-registers.rs:65:11
|
LL | asm!("li x18, 0");
| ^^^^^^^^^
Expand All @@ -35,7 +35,7 @@ LL | li x18, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:52:11
--> $DIR/riscv32e-registers.rs:69:11
|
LL | asm!("li x19, 0");
| ^^^^^^^^^
Expand All @@ -47,7 +47,7 @@ LL | li x19, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:55:11
--> $DIR/riscv32e-registers.rs:73:11
|
LL | asm!("li x20, 0");
| ^^^^^^^^^
Expand All @@ -59,7 +59,7 @@ LL | li x20, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:58:11
--> $DIR/riscv32e-registers.rs:77:11
|
LL | asm!("li x21, 0");
| ^^^^^^^^^
Expand All @@ -71,7 +71,7 @@ LL | li x21, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:61:11
--> $DIR/riscv32e-registers.rs:81:11
|
LL | asm!("li x22, 0");
| ^^^^^^^^^
Expand All @@ -83,7 +83,7 @@ LL | li x22, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:64:11
--> $DIR/riscv32e-registers.rs:85:11
|
LL | asm!("li x23, 0");
| ^^^^^^^^^
Expand All @@ -95,7 +95,7 @@ LL | li x23, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:67:11
--> $DIR/riscv32e-registers.rs:89:11
|
LL | asm!("li x24, 0");
| ^^^^^^^^^
Expand All @@ -107,7 +107,7 @@ LL | li x24, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:70:11
--> $DIR/riscv32e-registers.rs:93:11
|
LL | asm!("li x25, 0");
| ^^^^^^^^^
Expand All @@ -119,7 +119,7 @@ LL | li x25, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:73:11
--> $DIR/riscv32e-registers.rs:97:11
|
LL | asm!("li x26, 0");
| ^^^^^^^^^
Expand All @@ -131,7 +131,7 @@ LL | li x26, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:76:11
--> $DIR/riscv32e-registers.rs:101:11
|
LL | asm!("li x27, 0");
| ^^^^^^^^^
Expand All @@ -143,7 +143,7 @@ LL | li x27, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:79:11
--> $DIR/riscv32e-registers.rs:105:11
|
LL | asm!("li x28, 0");
| ^^^^^^^^^
Expand All @@ -155,7 +155,7 @@ LL | li x28, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:82:11
--> $DIR/riscv32e-registers.rs:109:11
|
LL | asm!("li x29, 0");
| ^^^^^^^^^
Expand All @@ -167,7 +167,7 @@ LL | li x29, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:85:11
--> $DIR/riscv32e-registers.rs:113:11
|
LL | asm!("li x30, 0");
| ^^^^^^^^^
Expand All @@ -179,7 +179,7 @@ LL | li x30, 0
| ^

error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:88:11
--> $DIR/riscv32e-registers.rs:117:11
|
LL | asm!("li x31, 0");
| ^^^^^^^^^
Expand Down
194 changes: 194 additions & 0 deletions tests/ui/asm/riscv/riscv32e-registers.riscv32e_llvm24.stderr
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,194 @@
error: register must be a GPR
--> $DIR/riscv32e-registers.rs:57:11
|
LL | asm!("li x16, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x16, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:61:11
|
LL | asm!("li x17, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x17, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:65:11
|
LL | asm!("li x18, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x18, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:69:11
|
LL | asm!("li x19, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x19, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:73:11
|
LL | asm!("li x20, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x20, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:77:11
|
LL | asm!("li x21, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x21, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:81:11
|
LL | asm!("li x22, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x22, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:85:11
|
LL | asm!("li x23, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x23, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:89:11
|
LL | asm!("li x24, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x24, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:93:11
|
LL | asm!("li x25, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x25, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:97:11
|
LL | asm!("li x26, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x26, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:101:11
|
LL | asm!("li x27, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x27, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:105:11
|
LL | asm!("li x28, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x28, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:109:11
|
LL | asm!("li x29, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x29, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:113:11
|
LL | asm!("li x30, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x30, 0
| ^

error: register must be a GPR
--> $DIR/riscv32e-registers.rs:117:11
|
LL | asm!("li x31, 0");
| ^^^^^^^^^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x31, 0
| ^

error: aborting due to 16 previous errors

Loading
Loading