Skip to content

riscv: update c-variadic test for LLVM changes #159089

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
rust-bors merged 1 commit into from
Jul 11, 2026
Merged

riscv: update c-variadic test for LLVM changes #159089

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
47 changes: 21 additions & 26 deletions tests/assembly-llvm/c-variadic/riscv.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -64,41 +64,37 @@ unsafe extern "C" fn read_i32(ap: &mut VaList<'_>) -> i32 {
// CHECK-LABEL: read_i32
//
// RISCV32: lw a2, 0(a0)
// RISCV32-NEXT: lw a1, 0(a2)
// RISCV32-NEXT: lw [[VAL:a[0-1]]], 0(a2)
// RISCV32-NEXT: addi a2, a2, 4
// RISCV32-NEXT: sw a2, 0(a0)
// RISCV32-NEXT: mv a0, a1
// RISCV32-NEXT: ret
// RISCV32-NEXT: sw a2, 0([[PTR:a[0-1]]])
// RISCV32: ret
//
// RISCV64: ld a2, 0(a0)
// RISCV64-NEXT: lw a1, 0(a2)
// RISCV64-NEXT: lw [[VAL:a[0-1]]], 0(a2)
// RISCV64-NEXT: addi a2, a2, 8
// RISCV64-NEXT: sd a2, 0(a0)
// RISCV64-NEXT: mv a0, a1
// RISCV64-NEXT: ret
// RISCV64-NEXT: sd a2, 0([[PTR:a[0-1]]])
// RISCV64: ret
va_arg(ap)
}

#[unsafe(no_mangle)]
unsafe extern "C" fn read_i64(ap: &mut VaList<'_>) -> i64 {
// CHECK-LABEL: read_i64
//
// RISCV32: lw a1, 0(a0)
// RISCV32-NEXT: addi a1, a1, 7
// RISCV32-NEXT: andi a3, a1, -8
// RISCV32-NEXT: lw a2, 0(a3)
// RISCV32: lw [[PTR:a[0-1]]], 0(a0)
// RISCV32-NEXT: addi [[PTR]], [[PTR]], 7
// RISCV32-NEXT: andi a3, [[PTR]], -8
// RISCV32-NEXT: lw [[LOW:a[02]]], 0(a3)
// RISCV32-NEXT: lw a1, 4(a3)
// RISCV32-NEXT: addi a3, a3, 8
// RISCV32-NEXT: sw a3, 0(a0)
// RISCV32-NEXT: mv a0, a2
// RISCV32-NEXT: ret
// RISCV32-NEXT: sw a3, 0([[LIST:a[02]]])
// RISCV32: ret
//
// RISCV64: ld a2, 0(a0)
// RISCV64-NEXT: ld a1, 0(a2)
// RISCV64-NEXT: ld [[VAL:a[0-1]]], 0(a2)
// RISCV64-NEXT: addi a2, a2, 8
// RISCV64-NEXT: sd a2, 0(a0)
// RISCV64-NEXT: mv a0, a1
// RISCV64-NEXT: ret
// RISCV64-NEXT: sd a2, 0([[PTR:a[0-1]]])
// RISCV64: ret
va_arg(ap)
}

Expand All @@ -107,15 +103,14 @@ unsafe extern "C" fn read_i64(ap: &mut VaList<'_>) -> i64 {
unsafe extern "C" fn read_i128(ap: &mut VaList<'_>) -> i128 {
// RISCV64-LABEL: read_i128
//
// RISCV64: ld a1, 0(a0)
// RISCV64-NEXT: addi a1, a1, 15
// RISCV64-NEXT: andi a3, a1, -16
// RISCV64-NEXT: ld a2, 0(a3)
// RISCV64: ld [[PTR:a[0-1]]], 0(a0)
// RISCV64-NEXT: addi [[PTR]], [[PTR]], 15
// RISCV64-NEXT: andi a3, [[PTR]], -16
// RISCV64-NEXT: ld [[LOW:a[02]]], 0(a3)
// RISCV64-NEXT: ld a1, 8(a3)
// RISCV64-NEXT: addi a3, a3, 16
// RISCV64-NEXT: sd a3, 0(a0)
// RISCV64-NEXT: mv a0, a2
// RISCV64-NEXT: ret
// RISCV64-NEXT: sd a3, 0([[LIST:a[02]]])
// RISCV64: ret
va_arg(ap)
}

Expand Down
Loading