stdarch subtree update

library/stdarch/.github/workflows/main.yml

@@ -285,12 +285,13 @@ jobs:
         include:
           - target: aarch64_be-unknown-linux-gnu
             build_std: true
-          - target: x86_64-unknown-linux-gnu
-            cc: icx
-            profile: dev
-          - target: x86_64-unknown-linux-gnu
-            cc: icx
-            profile: release
+          # getting the icx compiler hits network failures.
+          # - target: x86_64-unknown-linux-gnu
+          #   cc: icx
+          #   profile: dev
+          # - target: x86_64-unknown-linux-gnu
+          #   cc: icx
+          #   profile: release
         exclude:
           - target: armv7-unknown-linux-gnueabihf
             cc: gcc
@@ -318,7 +319,7 @@ jobs:
   # Check that the generated files agree with the checked-in versions.
   check-stdarch-gen:
     needs: [style]
-    name: Check stdarch-gen-{arm, loongarch, hexagon, hexagon-scalar} output
+    name: Check stdarch-gen-{arm, loongarch, hexagon} output
     runs-on: ubuntu-latest
     steps:
     - uses: actions/checkout@v6
@@ -342,11 +343,7 @@ jobs:
       run: |
         cargo run -p stdarch-gen-hexagon --release
         git diff --exit-code
-    - name: Check hexagon scalar
-      run: |
-        cargo run -p stdarch-gen-hexagon-scalar --release
-        git diff --exit-code
-
+
   # Run some tests with Miri. Most stdarch functions use platform-specific intrinsics
   # that Miri does not support. Also Miri is reltively slow.
   #

library/stdarch/Cargo.lock

@@ -849,13 +849,6 @@ dependencies = [
  "stdarch-gen-common",
 ]
 
-[[package]]
-name = "stdarch-gen-hexagon-scalar"
-version = "0.1.0"
-dependencies = [
- "regex",
-]
-
 [[package]]
 name = "stdarch-gen-loongarch"
 version = "0.1.0"
@@ -869,7 +862,6 @@ version = "0.1.0"
 dependencies = [
  "assert-instr-macro",
  "cc",
- "cfg-if",
  "rustc-demangle",
  "simd-test-macro",
  "wasmprinter",

library/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile

@@ -11,13 +11,13 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   xz-utils \
   wget
 
-RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
+RUN wget https://ci-mirrors.rust-lang.org/llvm/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
 RUN mkdir llvm
 RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm
 
 ENV CLANG_PATH="/llvm/bin/clang"
 ENV GCC_PATH=aarch64-linux-gnu-gcc
 
 ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER=aarch64-linux-gnu-gcc \
-    CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64 -cpu max -L /usr/aarch64-linux-gnu" \
+    CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER="qemu-aarch64 -cpu max,sve512=on -L /usr/aarch64-linux-gnu" \
     OBJDUMP=aarch64-linux-gnu-objdump

library/stdarch/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile

@@ -19,7 +19,7 @@ RUN curl -L "https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/bin
 RUN tar -xvf "${TOOLCHAIN}.tar.xz"
 RUN mkdir /toolchains && mv "./${TOOLCHAIN}" /toolchains
 
-RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
+RUN wget https://ci-mirrors.rust-lang.org/llvm/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
 RUN mkdir llvm
 RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm
 

library/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile

@@ -10,7 +10,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   file \
   wget
 
-RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
+RUN wget https://ci-mirrors.rust-lang.org/llvm/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
 RUN mkdir llvm
 RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm
 

library/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile

@@ -13,7 +13,7 @@ RUN wget http://ci-mirrors.rust-lang.org/sde-external-10.8.0-2026-03-15-lin.tar.
 RUN mkdir intel-sde
 RUN tar -xJf sde.tar.xz --strip-components=1 -C intel-sde
 
-RUN wget https://mirrors.edge.kernel.org/pub/tools/llvm/files/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
+RUN wget https://ci-mirrors.rust-lang.org/llvm/llvm-22.1.4-x86_64.tar.gz -O llvm.tar.xz
 RUN mkdir llvm
 RUN tar -xvf llvm.tar.xz --strip-components=1 -C llvm
 

library/stdarch/ci/intrinsic-test.sh

@@ -45,21 +45,25 @@ case ${TARGET} in
     aarch64_be*)
         export CFLAGS="-I${AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc/usr/include --sysroot={AARCH64_BE_TOOLCHAIN}/aarch64_be-none-linux-gnu/libc -Wno-nonportable-vector-initialization"
         ARCH=aarch64_be
+        RUNTIME_RUSTFLAGS=
         ;;
 
     aarch64*)
         export CFLAGS="-I/usr/aarch64-linux-gnu/include/"
         ARCH=aarch64
+        RUNTIME_RUSTFLAGS=-Ctarget-feature=+sve,+sve2
         ;;
 
     armv7*)
         export CFLAGS="-I/usr/arm-linux-gnueabihf/include/"
         ARCH=arm
+        RUNTIME_RUSTFLAGS=
         ;;
 
     x86_64*)
         export CFLAGS="-I/usr/include/x86_64-linux-gnu/"
         ARCH=x86
+        RUNTIME_RUSTFLAGS=
         ;;
     *)
         ;;
@@ -86,5 +90,5 @@ case "${TARGET}" in
         ;;
 esac
 
-cargo test --manifest-path=rust_programs/Cargo.toml --target "${TARGET}" --profile "${PROFILE}" \
-    --tests "$@"
+RUSTFLAGS="${RUNTIME_RUSTFLAGS}" cargo test --manifest-path=rust_programs/Cargo.toml \
+    --target "${TARGET}" --profile "${PROFILE}" --tests --no-fail-fast "$@"

library/stdarch/crates/core_arch/src/aarch64/sve/generated.rs

@@ -42211,30 +42211,17 @@ pub fn svtmad_f64<const IMM3: i32>(op1: svfloat64_t, op2: svfloat64_t) -> svfloa
     unsafe { _svtmad_f64(op1, op2, IMM3) }
 }
 #[doc = "Interleave even elements from two inputs"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b8)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(trn1))]
-pub fn svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i1")]
-        fn _svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
-    }
-    unsafe { _svtrn1_b8(op1, op2) }
-}
-#[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b16)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn1))]
 pub fn svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv8i1")]
-        fn _svtrn1_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.b16")]
+        fn _svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn1_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn1_b16(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b32)"]
@@ -42244,10 +42231,10 @@ pub fn svtrn1_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(trn1))]
 pub fn svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv4i1")]
-        fn _svtrn1_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.b32")]
+        fn _svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn1_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn1_b32(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1_b64)"]
@@ -42257,10 +42244,10 @@ pub fn svtrn1_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(trn1))]
 pub fn svtrn1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv2i1")]
-        fn _svtrn1_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.b64")]
+        fn _svtrn1_b64(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn1_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn1_b64(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave even elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_f32])"]
@@ -42376,6 +42363,19 @@ pub fn svtrn1_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 pub fn svtrn1_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svtrn1_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
+#[doc = "Interleave even elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1[_b8])"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn1))]
+pub fn svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn1.nxv16i1")]
+        fn _svtrn1_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svtrn1_b8(op1, op2) }
+}
 #[doc = "Interleave even quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn1q[_f32])"]
 #[inline]
@@ -42491,30 +42491,17 @@ pub fn svtrn1q_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svtrn1q_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
 #[doc = "Interleave odd elements from two inputs"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b8)"]
-#[inline]
-#[target_feature(enable = "sve")]
-#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
-#[cfg_attr(test, assert_instr(trn2))]
-pub fn svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
-    unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i1")]
-        fn _svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
-    }
-    unsafe { _svtrn2_b8(op1, op2) }
-}
-#[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b16)"]
 #[inline]
 #[target_feature(enable = "sve")]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 #[cfg_attr(test, assert_instr(trn2))]
 pub fn svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv8i1")]
-        fn _svtrn2_b16(op1: svbool8_t, op2: svbool8_t) -> svbool8_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.b16")]
+        fn _svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn2_b16(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn2_b16(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b32)"]
@@ -42524,10 +42511,10 @@ pub fn svtrn2_b16(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(trn2))]
 pub fn svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv4i1")]
-        fn _svtrn2_b32(op1: svbool4_t, op2: svbool4_t) -> svbool4_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.b32")]
+        fn _svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn2_b32(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn2_b32(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2_b64)"]
@@ -42537,10 +42524,10 @@ pub fn svtrn2_b32(op1: svbool_t, op2: svbool_t) -> svbool_t {
 #[cfg_attr(test, assert_instr(trn2))]
 pub fn svtrn2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t {
     unsafe extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv2i1")]
-        fn _svtrn2_b64(op1: svbool2_t, op2: svbool2_t) -> svbool2_t;
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.b64")]
+        fn _svtrn2_b64(op1: svbool_t, op2: svbool_t) -> svbool_t;
     }
-    unsafe { _svtrn2_b64(op1.sve_into(), op2.sve_into()).sve_into() }
+    unsafe { _svtrn2_b64(op1.sve_into(), op2.sve_into()) }
 }
 #[doc = "Interleave odd elements from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_f32])"]
@@ -42656,6 +42643,19 @@ pub fn svtrn2_u32(op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
 pub fn svtrn2_u64(op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
     unsafe { svtrn2_s64(op1.as_signed(), op2.as_signed()).as_unsigned() }
 }
+#[doc = "Interleave odd elements from two inputs"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2[_b8])"]
+#[inline]
+#[target_feature(enable = "sve")]
+#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
+#[cfg_attr(test, assert_instr(trn2))]
+pub fn svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.trn2.nxv16i1")]
+        fn _svtrn2_b8(op1: svbool_t, op2: svbool_t) -> svbool_t;
+    }
+    unsafe { _svtrn2_b8(op1, op2) }
+}
 #[doc = "Interleave odd quadwords from two inputs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svtrn2q[_f32])"]
 #[inline]

library/stdarch/crates/core_arch/src/hexagon/scalar.rs

@@ -1,3 +1,4 @@
+// This code is automatically generated. DO NOT MODIFY.
 //! Hexagon scalar intrinsics
 //!
 //! This module provides intrinsics for scalar (non-HVX) Hexagon DSP operations,