clarify simd_relaxed_fma non-determinism

[RalfJung]

This is the safer spec in the sense that it is more likely to be satisfied by the backend -- and if people are okay with a non-deterministic result, I assume they don't care whether it's the same choice across all lanes or not?

Cc @calebzulawski @workingjubilee

[rustbot]

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[rustbot]

Some changes occurred to the platform-builtins intrinsics. Make sure the
LLVM backend as well as portable-simd gets adapted for the changes.

cc @antoyo, @GuillaumeGomez, @bjorn3, @calebzulawski, @programmerjake

Some changes occurred to the intrinsics. Make sure the CTFE / Miri interpreter
gets adapted for the changes, if necessary.

cc @rust-lang/miri, @rust-lang/wg-const-eval

[workingjubilee]

headscratch Hmm. That would be kinda weird? I see your point, but it's a bit odd.

[RalfJung]

It matches the usual principle that a SIMD op id equivalent to the corresponding scar op in a loop.

[workingjubilee]

Hm.

Apparently the version implemented by wasm's "Relaxed SIMD" is actually quite strict, where the nondeterministic choice is quite early: WebAssembly/relaxed-simd@c3f9359

It's still valid to lower a lax semantic to a stricter one, however, so having given it some more thought, this seems fine. LLVM indeed does not specify!

I would never expect this to happen to a "natural" vector (pow2 elements, etc.) but I could definitely see it happening to a "packed" one... say, Simd<f32, 5>? A valid interpretation would be for operations to work as if decomposed to operating on the fields of this:

#[repr(packed(4))]
struct LoweredSimd {
    fvec: Simd<f32, 4>,
    single: f32,
}

Then perhaps the code generation uses a libcall to fmaf, or just an FMA instruction, for the single f32, but then operates on the fvec using plain mul, then add. And I don't see any use in specifying which float is the odd one out.

@bors r+

[bors]

📌 Commit f4217f4 has been approved by workingjubilee

It is now in the queue for this repository.