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RISC-V LLVM feature +unaligned-scalar-mem not recognized by rustc #110883

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korran opened this issue Apr 27, 2023 · 0 comments · Fixed by #110884
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RISC-V LLVM feature +unaligned-scalar-mem not recognized by rustc #110883

korran opened this issue Apr 27, 2023 · 0 comments · Fixed by #110884
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A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. O-riscv Target: RISC-V architecture

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@korran
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korran commented Apr 27, 2023

Example

// Compile with rustc --target riscv32imc-unknown-none-elf -C target-feature=+unaligned-scalar-mem --emit=obj
#![no_std]
#![no_main]

use core::panic::PanicInfo;

#[panic_handler]
fn panic(_info: &PanicInfo) -> ! {
    loop {}
}

Current output

warning: unknown feature specified for `-Ctarget-feature`: `unaligned-scalar-mem`
  |
  = note: it is still passed through to the codegen backend
  = help: consider filing a feature request

warning: 1 warning emitted

Desired output

No warning

Background / Rationale

Some RISC-V cores support unaligned access to memory without trapping. On such cores, the compiler could significantly improve code-size and performance when using functions like core::ptr::read_unaligned by emitting a single load or store instruction with an unaligned address, rather than a long sequence of byte-sized load/store/bitmanip instructions.

I need to use the unaligned-scalar-mem target feature to improve code-size and performance. When I set the flag -C target-feature=+unaligned-scalar-mem, LLVM successfully recognizes the target feature and generates the desired machine code, but rustc prints out the warning above, and I can't figure out how to disable it.

@jyn514 jyn514 added A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. O-riscv Target: RISC-V architecture A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. labels May 5, 2023
Dylan-DPC added a commit to Dylan-DPC/rust that referenced this issue May 18, 2023
…leywiser

Support RISC-V unaligned-scalar-mem target feature

This adds `unaligned-scalar-mem` as an allowed RISC-V target feature. Some RISC-V cores support unaligned access to memory without trapping. On such cores, the compiler could significantly improve code-size and performance when using functions like core::ptr::read_unaligned<u32> by emitting a single load or store instruction with an unaligned address, rather than a long sequence of byte load/store/bitmanip instructions.

Enabling the `unaligned-scalar-mem` target feature allows LLVM to do this optimization.

Fixes rust-lang#110883
@bors bors closed this as completed in 08f7e32 May 18, 2023
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Labels
A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. O-riscv Target: RISC-V architecture
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