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[AArch64][SVE] Asm: Support for ADR instruction.
Supporting various addressing modes: - adr z0.s, [z0.s, z0.s] - adr z0.s, [z0.s, z0.s, lsl #<shift>] - adr z0.d, [z0.d, z0.d] - adr z0.d, [z0.d, z0.d, lsl #<shift>] - adr z0.d, [z0.d, z0.d, uxtw #<shift>] - adr z0.d, [z0.d, z0.d, sxtw #<shift>] Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D48870 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336533 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/AArch64/AArch64RegisterInfo.td‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1062,17 +1062,17 @@ foreach RegWidth = [32, 64] in {
10621062
def ZPR#RegWidth#ExtSXTW16 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 16>;
10631063
def ZPR#RegWidth#ExtSXTW32 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 32>;
10641064
def ZPR#RegWidth#ExtSXTW64 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 64>;
1065-
}
10661065

1067-
// LSL(8|16|32|64)
1068-
def ZPR64AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", 64, 8>;
1069-
def ZPR64AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", 64, 16>;
1070-
def ZPR64AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", 64, 32>;
1071-
def ZPR64AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", 64, 64>;
1072-
def ZPR64ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 8>;
1073-
def ZPR64ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 16>;
1074-
def ZPR64ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 32>;
1075-
def ZPR64ExtLSL64 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 64>;
1066+
// LSL(8|16|32|64)
1067+
def ZPR#RegWidth#AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", RegWidth, 8>;
1068+
def ZPR#RegWidth#AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", RegWidth, 16>;
1069+
def ZPR#RegWidth#AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", RegWidth, 32>;
1070+
def ZPR#RegWidth#AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", RegWidth, 64>;
1071+
def ZPR#RegWidth#ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 8>;
1072+
def ZPR#RegWidth#ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 16>;
1073+
def ZPR#RegWidth#ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 32>;
1074+
def ZPR#RegWidth#ExtLSL64 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 64>;
1075+
}
10761076

10771077
class GPR64ShiftExtendAsmOperand <string AsmOperandName, int Scale, string RegClass> : AsmOperandClass {
10781078
let Name = AsmOperandName # Scale;

‎lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -534,6 +534,11 @@ let Predicates = [HasSVE] in {
534534
defm PRFW_D_PZI : sve_mem_64b_prfm_vi<0b10, "prfw", uimm5s4>;
535535
defm PRFD_D_PZI : sve_mem_64b_prfm_vi<0b11, "prfd", uimm5s8>;
536536

537+
defm ADR_SXTW_ZZZ_D : sve_int_bin_cons_misc_0_a_sxtw<0b00, "adr">;
538+
defm ADR_UXTW_ZZZ_D : sve_int_bin_cons_misc_0_a_uxtw<0b01, "adr">;
539+
defm ADR_LSL_ZZZ_S : sve_int_bin_cons_misc_0_a_32_lsl<0b10, "adr">;
540+
defm ADR_LSL_ZZZ_D : sve_int_bin_cons_misc_0_a_64_lsl<0b11, "adr">;
541+
537542
defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
538543
defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
539544
defm UZP1_ZZZ : sve_int_perm_bin_perm_zz<0b010, "uzp1">;

‎lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 21 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2390,14 +2390,17 @@ AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
23902390
SMLoc S = getLoc();
23912391
const MCExpr *Expr;
23922392

2393-
parseOptionalToken(AsmToken::Hash);
2394-
if (getParser().parseExpression(Expr))
2395-
return MatchOperand_ParseFail;
2393+
const AsmToken &Tok = getParser().getTok();
2394+
if (parseOptionalToken(AsmToken::Hash) || Tok.is(AsmToken::Integer)) {
2395+
if (getParser().parseExpression(Expr))
2396+
return MatchOperand_ParseFail;
23962397

2397-
SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
2398-
Operands.push_back(AArch64Operand::CreateImm(Expr, S, E, getContext()));
2398+
SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
2399+
Operands.push_back(AArch64Operand::CreateImm(Expr, S, E, getContext()));
23992400

2400-
return MatchOperand_Success;
2401+
return MatchOperand_Success;
2402+
}
2403+
return MatchOperand_NoMatch;
24012404
}
24022405

24032406
/// tryParseFPImm - A floating point immediate expression operand.
@@ -4127,6 +4130,14 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
41274130
case Match_InvalidZPR64UXTW64:
41284131
case Match_InvalidZPR64SXTW64:
41294132
return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'");
4133+
case Match_InvalidZPR32LSL8:
4134+
return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].s'");
4135+
case Match_InvalidZPR32LSL16:
4136+
return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].s, lsl #1'");
4137+
case Match_InvalidZPR32LSL32:
4138+
return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].s, lsl #2'");
4139+
case Match_InvalidZPR32LSL64:
4140+
return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].s, lsl #3'");
41304141
case Match_InvalidZPR64LSL8:
41314142
return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d'");
41324143
case Match_InvalidZPR64LSL16:
@@ -4653,6 +4664,10 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
46534664
case Match_InvalidZPR64SXTW32:
46544665
case Match_InvalidZPR64UXTW64:
46554666
case Match_InvalidZPR64SXTW64:
4667+
case Match_InvalidZPR32LSL8:
4668+
case Match_InvalidZPR32LSL16:
4669+
case Match_InvalidZPR32LSL32:
4670+
case Match_InvalidZPR32LSL64:
46564671
case Match_InvalidZPR64LSL8:
46574672
case Match_InvalidZPR64LSL16:
46584673
case Match_InvalidZPR64LSL32:

‎lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2989,3 +2989,55 @@ multiclass sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
29892989
def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
29902990
(!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
29912991
}
2992+
2993+
2994+
//===----------------------------------------------------------------------===//
2995+
// SVE Compute Vector Address Group
2996+
//===----------------------------------------------------------------------===//
2997+
2998+
class sve_int_bin_cons_misc_0_a<bits<2> opc, bits<2> msz, string asm,
2999+
ZPRRegOp zprty, RegisterOperand zprext>
3000+
: I<(outs zprty:$Zd), (ins zprty:$Zn, zprext:$Zm),
3001+
asm, "\t$Zd, [$Zn, $Zm]",
3002+
"",
3003+
[]>, Sched<[]> {
3004+
bits<5> Zd;
3005+
bits<5> Zn;
3006+
bits<5> Zm;
3007+
let Inst{31-24} = 0b00000100;
3008+
let Inst{23-22} = opc;
3009+
let Inst{21} = 0b1;
3010+
let Inst{20-16} = Zm;
3011+
let Inst{15-12} = 0b1010;
3012+
let Inst{11-10} = msz;
3013+
let Inst{9-5} = Zn;
3014+
let Inst{4-0} = Zd;
3015+
}
3016+
3017+
multiclass sve_int_bin_cons_misc_0_a_uxtw<bits<2> opc, string asm> {
3018+
def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtUXTW8>;
3019+
def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtUXTW16>;
3020+
def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtUXTW32>;
3021+
def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtUXTW64>;
3022+
}
3023+
3024+
multiclass sve_int_bin_cons_misc_0_a_sxtw<bits<2> opc, string asm> {
3025+
def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtSXTW8>;
3026+
def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtSXTW16>;
3027+
def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtSXTW32>;
3028+
def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtSXTW64>;
3029+
}
3030+
3031+
multiclass sve_int_bin_cons_misc_0_a_32_lsl<bits<2> opc, string asm> {
3032+
def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR32, ZPR32ExtLSL8>;
3033+
def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR32, ZPR32ExtLSL16>;
3034+
def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR32, ZPR32ExtLSL32>;
3035+
def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR32, ZPR32ExtLSL64>;
3036+
}
3037+
3038+
multiclass sve_int_bin_cons_misc_0_a_64_lsl<bits<2> opc, string asm> {
3039+
def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtLSL8>;
3040+
def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtLSL16>;
3041+
def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtLSL32>;
3042+
def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtLSL64>;
3043+
}

‎test/MC/AArch64/SVE/adr-diagnostics.s‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Invalid addressing modes.
5+
6+
adr z0.s, [z0.s, z0.d]
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8+
// CHECK-NEXT: adr z0.s, [z0.s, z0.d]
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
adr z0.s, [z0.s, z0.s, lsl]
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
13+
// CHECK-NEXT: adr z0.s, [z0.s, z0.s, lsl]
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
adr z0.s, [z0.s, z0.s, lsl #4]
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s'
18+
// CHECK-NEXT: adr z0.s, [z0.s, z0.s, lsl #4]
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
adr z0.s, [z0.s, z0.s, uxtw]
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s'
23+
// CHECK-NEXT: adr z0.s, [z0.s, z0.s, uxtw]
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
adr z0.s, [z0.s, z0.s, sxtw]
27+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s'
28+
// CHECK-NEXT: adr z0.s, [z0.s, z0.s, sxtw]
29+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30+
31+
adr z0.d, [z0.d, z0.s]
32+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
33+
// CHECK-NEXT: adr z0.d, [z0.d, z0.s]
34+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
35+
36+
adr z0.d, [z0.d, z0.s, uxtw]
37+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
38+
// CHECK-NEXT: adr z0.d, [z0.d, z0.s, uxtw]
39+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
40+
41+
adr z0.d, [z0.d, z0.s, sxtw]
42+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
43+
// CHECK-NEXT: adr z0.d, [z0.d, z0.s, sxtw]
44+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
45+
46+
adr z0.d, [z0.d, z0.d, lsl #4]
47+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
48+
// CHECK-NEXT: adr z0.d, [z0.d, z0.d, lsl #4]
49+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
50+
51+
adr z0.d, [z0.d, z0.d, uxtw #4]
52+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
53+
// CHECK-NEXT: adr z0.d, [z0.d, z0.d, uxtw #4]
54+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
55+
56+
adr z0.d, [z0.d, z0.d, sxtw #4]
57+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
58+
// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #4]
59+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎test/MC/AArch64/SVE/adr.s‎

Lines changed: 128 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,128 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
6+
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
10+
adr z0.s, [z0.s, z0.s]
11+
// CHECK-INST: adr z0.s, [z0.s, z0.s]
12+
// CHECK-ENCODING: [0x00,0xa0,0xa0,0x04]
13+
// CHECK-ERROR: instruction requires: sve
14+
// CHECK-UNKNOWN: 00 a0 a0 04 <unknown>
15+
16+
adr z0.s, [z0.s, z0.s, lsl #0]
17+
// CHECK-INST: adr z0.s, [z0.s, z0.s]
18+
// CHECK-ENCODING: [0x00,0xa0,0xa0,0x04]
19+
// CHECK-ERROR: instruction requires: sve
20+
// CHECK-UNKNOWN: 00 a0 a0 04 <unknown>
21+
22+
adr z0.s, [z0.s, z0.s, lsl #1]
23+
// CHECK-INST: adr z0.s, [z0.s, z0.s, lsl #1]
24+
// CHECK-ENCODING: [0x00,0xa4,0xa0,0x04]
25+
// CHECK-ERROR: instruction requires: sve
26+
// CHECK-UNKNOWN: 00 a4 a0 04 <unknown>
27+
28+
adr z0.s, [z0.s, z0.s, lsl #2]
29+
// CHECK-INST: adr z0.s, [z0.s, z0.s, lsl #2]
30+
// CHECK-ENCODING: [0x00,0xa8,0xa0,0x04]
31+
// CHECK-ERROR: instruction requires: sve
32+
// CHECK-UNKNOWN: 00 a8 a0 04 <unknown>
33+
34+
adr z0.s, [z0.s, z0.s, lsl #3]
35+
// CHECK-INST: adr z0.s, [z0.s, z0.s, lsl #3]
36+
// CHECK-ENCODING: [0x00,0xac,0xa0,0x04]
37+
// CHECK-ERROR: instruction requires: sve
38+
// CHECK-UNKNOWN: 00 ac a0 04 <unknown>
39+
40+
adr z0.d, [z0.d, z0.d]
41+
// CHECK-INST: adr z0.d, [z0.d, z0.d]
42+
// CHECK-ENCODING: [0x00,0xa0,0xe0,0x04]
43+
// CHECK-ERROR: instruction requires: sve
44+
// CHECK-UNKNOWN: 00 a0 e0 04 <unknown>
45+
46+
adr z0.d, [z0.d, z0.d, lsl #0]
47+
// CHECK-INST: adr z0.d, [z0.d, z0.d]
48+
// CHECK-ENCODING: [0x00,0xa0,0xe0,0x04]
49+
// CHECK-ERROR: instruction requires: sve
50+
// CHECK-UNKNOWN: 00 a0 e0 04 <unknown>
51+
52+
adr z0.d, [z0.d, z0.d, lsl #1]
53+
// CHECK-INST: adr z0.d, [z0.d, z0.d, lsl #1]
54+
// CHECK-ENCODING: [0x00,0xa4,0xe0,0x04]
55+
// CHECK-ERROR: instruction requires: sve
56+
// CHECK-UNKNOWN: 00 a4 e0 04 <unknown>
57+
58+
adr z0.d, [z0.d, z0.d, lsl #2]
59+
// CHECK-INST: adr z0.d, [z0.d, z0.d, lsl #2]
60+
// CHECK-ENCODING: [0x00,0xa8,0xe0,0x04]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: 00 a8 e0 04 <unknown>
63+
64+
adr z0.d, [z0.d, z0.d, lsl #3]
65+
// CHECK-INST: adr z0.d, [z0.d, z0.d, lsl #3]
66+
// CHECK-ENCODING: [0x00,0xac,0xe0,0x04]
67+
// CHECK-ERROR: instruction requires: sve
68+
// CHECK-UNKNOWN: 00 ac e0 04 <unknown>
69+
70+
adr z0.d, [z0.d, z0.d, uxtw]
71+
// CHECK-INST: adr z0.d, [z0.d, z0.d, uxtw]
72+
// CHECK-ENCODING: [0x00,0xa0,0x60,0x04]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: 00 a0 60 04 <unknown>
75+
76+
adr z0.d, [z0.d, z0.d, uxtw #0]
77+
// CHECK-INST: adr z0.d, [z0.d, z0.d, uxtw]
78+
// CHECK-ENCODING: [0x00,0xa0,0x60,0x04]
79+
// CHECK-ERROR: instruction requires: sve
80+
// CHECK-UNKNOWN: 00 a0 60 04 <unknown>
81+
82+
adr z0.d, [z0.d, z0.d, uxtw #1]
83+
// CHECK-INST: adr z0.d, [z0.d, z0.d, uxtw #1]
84+
// CHECK-ENCODING: [0x00,0xa4,0x60,0x04]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 00 a4 60 04 <unknown>
87+
88+
adr z0.d, [z0.d, z0.d, uxtw #2]
89+
// CHECK-INST: adr z0.d, [z0.d, z0.d, uxtw #2]
90+
// CHECK-ENCODING: [0x00,0xa8,0x60,0x04]
91+
// CHECK-ERROR: instruction requires: sve
92+
// CHECK-UNKNOWN: 00 a8 60 04 <unknown>
93+
94+
adr z0.d, [z0.d, z0.d, uxtw #3]
95+
// CHECK-INST: adr z0.d, [z0.d, z0.d, uxtw #3]
96+
// CHECK-ENCODING: [0x00,0xac,0x60,0x04]
97+
// CHECK-ERROR: instruction requires: sve
98+
// CHECK-UNKNOWN: 00 ac 60 04 <unknown>
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adr z0.d, [z0.d, z0.d, sxtw]
101+
// CHECK-INST: adr z0.d, [z0.d, z0.d, sxtw]
102+
// CHECK-ENCODING: [0x00,0xa0,0x20,0x04]
103+
// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 a0 20 04 <unknown>
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adr z0.d, [z0.d, z0.d, sxtw #0]
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// CHECK-INST: adr z0.d, [z0.d, z0.d, sxtw]
108+
// CHECK-ENCODING: [0x00,0xa0,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 a0 20 04 <unknown>
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adr z0.d, [z0.d, z0.d, sxtw #1]
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// CHECK-INST: adr z0.d, [z0.d, z0.d, sxtw #1]
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// CHECK-ENCODING: [0x00,0xa4,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 a4 20 04 <unknown>
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adr z0.d, [z0.d, z0.d, sxtw #2]
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// CHECK-INST: adr z0.d, [z0.d, z0.d, sxtw #2]
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// CHECK-ENCODING: [0x00,0xa8,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 a8 20 04 <unknown>
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adr z0.d, [z0.d, z0.d, sxtw #3]
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// CHECK-INST: adr z0.d, [z0.d, z0.d, sxtw #3]
126+
// CHECK-ENCODING: [0x00,0xac,0x20,0x04]
127+
// CHECK-ERROR: instruction requires: sve
128+
// CHECK-UNKNOWN: 00 ac 20 04 <unknown>

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