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[AArch64][SVE] Asm: Support for UZP and TRN instructions.
This patch adds support for: UZP1 Concatenate even elements from two vectors UZP2 Concatenate odd elements from two vectors TRN1 Interleave even elements from two vectors TRN2 Interleave odd elements from two vectors With variants for both data and predicate vectors, e.g. uzp1 z0.b, z1.b, z2.b trn2 p0.s, p1.s, p2.s git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336531 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -536,9 +536,17 @@ let Predicates = [HasSVE] in {
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537537
defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
538538
defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
539+
defm UZP1_ZZZ : sve_int_perm_bin_perm_zz<0b010, "uzp1">;
540+
defm UZP2_ZZZ : sve_int_perm_bin_perm_zz<0b011, "uzp2">;
541+
defm TRN1_ZZZ : sve_int_perm_bin_perm_zz<0b100, "trn1">;
542+
defm TRN2_ZZZ : sve_int_perm_bin_perm_zz<0b101, "trn2">;
539543

540544
defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">;
541545
defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">;
546+
defm UZP1_PPP : sve_int_perm_bin_perm_pp<0b010, "uzp1">;
547+
defm UZP2_PPP : sve_int_perm_bin_perm_pp<0b011, "uzp2">;
548+
defm TRN1_PPP : sve_int_perm_bin_perm_pp<0b100, "trn1">;
549+
defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2">;
542550

543551
def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">;
544552
def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">;

‎test/MC/AArch64/SVE/trn1-diagnostics.s‎

Lines changed: 43 additions & 0 deletions
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@@ -0,0 +1,43 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
2+
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// Invalid element kind.
4+
trn1 z10.h, z22.h, z31.x
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
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// CHECK-NEXT: trn1 z10.h, z22.h, z31.x
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8+
9+
// Element size specifiers should match.
10+
trn1 z10.h, z3.h, z15.b
11+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
12+
// CHECK-NEXT: trn1 z10.h, z3.h, z15.b
13+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
14+
15+
// Too few operands
16+
trn1 z1.h, z2.h
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
18+
// CHECK-NEXT: trn1 z1.h, z2.h
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
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// z32 is not a valid SVE data register
22+
trn1 z1.s, z2.s, z32.s
23+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
24+
// CHECK-NEXT: trn1 z1.s, z2.s, z32.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26+
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// p16 is not a valid SVE predicate register
28+
trn1 p1.s, p2.s, p16.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30+
// CHECK-NEXT: trn1 p1.s, p2.s, p16.s
31+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32+
33+
// Combining data and predicate registers as operands
34+
trn1 z1.s, z2.s, p3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
36+
// CHECK-NEXT: trn1 z1.s, z2.s, p3.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38+
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// Combining predicate and data registers as operands
40+
trn1 p1.s, p2.s, z3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
42+
// CHECK-NEXT: trn1 p1.s, p2.s, z3.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎test/MC/AArch64/SVE/trn1.s‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
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trn1 z31.b, z31.b, z31.b
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// CHECK-INST: trn1 z31.b, z31.b, z31.b
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// CHECK-ENCODING: [0xff,0x73,0x3f,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 73 3f 05 <unknown>
15+
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trn1 z31.h, z31.h, z31.h
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// CHECK-INST: trn1 z31.h, z31.h, z31.h
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// CHECK-ENCODING: [0xff,0x73,0x7f,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 73 7f 05 <unknown>
21+
22+
trn1 z31.s, z31.s, z31.s
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// CHECK-INST: trn1 z31.s, z31.s, z31.s
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// CHECK-ENCODING: [0xff,0x73,0xbf,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 73 bf 05 <unknown>
27+
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trn1 z31.d, z31.d, z31.d
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// CHECK-INST: trn1 z31.d, z31.d, z31.d
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// CHECK-ENCODING: [0xff,0x73,0xff,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 73 ff 05 <unknown>
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trn1 p15.b, p15.b, p15.b
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// CHECK-INST: trn1 p15.b, p15.b, p15.b
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// CHECK-ENCODING: [0xef,0x51,0x2f,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ef 51 2f 05 <unknown>
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trn1 p15.s, p15.s, p15.s
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// CHECK-INST: trn1 p15.s, p15.s, p15.s
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// CHECK-ENCODING: [0xef,0x51,0xaf,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ef 51 af 05 <unknown>
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trn1 p15.h, p15.h, p15.h
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// CHECK-INST: trn1 p15.h, p15.h, p15.h
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// CHECK-ENCODING: [0xef,0x51,0x6f,0x05]
49+
// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ef 51 6f 05 <unknown>
51+
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trn1 p15.d, p15.d, p15.d
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// CHECK-INST: trn1 p15.d, p15.d, p15.d
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// CHECK-ENCODING: [0xef,0x51,0xef,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ef 51 ef 05 <unknown>

‎test/MC/AArch64/SVE/trn2-diagnostics.s‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
2+
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// Invalid element kind.
4+
trn2 z6.h, z23.h, z31.x
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
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// CHECK-NEXT: trn2 z6.h, z23.h, z31.x
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8+
9+
// Element size specifiers should match.
10+
trn2 z0.h, z30.h, z24.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: trn2 z0.h, z30.h, z24.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Too few operands
16+
trn2 z1.h, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
18+
// CHECK-NEXT: trn2 z1.h, z2.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
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// z32 is not a valid SVE data register
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trn2 z1.s, z2.s, z32.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
24+
// CHECK-NEXT: trn2 z1.s, z2.s, z32.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26+
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// p16 is not a valid SVE predicate register
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trn2 p1.s, p2.s, p16.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30+
// CHECK-NEXT: trn2 p1.s, p2.s, p16.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32+
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// Combining data and predicate registers as operands
34+
trn2 z1.s, z2.s, p3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
36+
// CHECK-NEXT: trn2 z1.s, z2.s, p3.s
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38+
39+
// Combining predicate and data registers as operands
40+
trn2 p1.s, p2.s, z3.s
41+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
42+
// CHECK-NEXT: trn2 p1.s, p2.s, z3.s
43+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎test/MC/AArch64/SVE/trn2.s‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
6+
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
10+
trn2 z31.b, z31.b, z31.b
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// CHECK-INST: trn2 z31.b, z31.b, z31.b
12+
// CHECK-ENCODING: [0xff,0x77,0x3f,0x05]
13+
// CHECK-ERROR: instruction requires: sve
14+
// CHECK-UNKNOWN: ff 77 3f 05 <unknown>
15+
16+
trn2 z31.h, z31.h, z31.h
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// CHECK-INST: trn2 z31.h, z31.h, z31.h
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// CHECK-ENCODING: [0xff,0x77,0x7f,0x05]
19+
// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 77 7f 05 <unknown>
21+
22+
trn2 z31.s, z31.s, z31.s
23+
// CHECK-INST: trn2 z31.s, z31.s, z31.s
24+
// CHECK-ENCODING: [0xff,0x77,0xbf,0x05]
25+
// CHECK-ERROR: instruction requires: sve
26+
// CHECK-UNKNOWN: ff 77 bf 05 <unknown>
27+
28+
trn2 z31.d, z31.d, z31.d
29+
// CHECK-INST: trn2 z31.d, z31.d, z31.d
30+
// CHECK-ENCODING: [0xff,0x77,0xff,0x05]
31+
// CHECK-ERROR: instruction requires: sve
32+
// CHECK-UNKNOWN: ff 77 ff 05 <unknown>
33+
34+
trn2 p15.b, p15.b, p15.b
35+
// CHECK-INST: trn2 p15.b, p15.b, p15.b
36+
// CHECK-ENCODING: [0xef,0x55,0x2f,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ef 55 2f 05 <unknown>
39+
40+
trn2 p15.s, p15.s, p15.s
41+
// CHECK-INST: trn2 p15.s, p15.s, p15.s
42+
// CHECK-ENCODING: [0xef,0x55,0xaf,0x05]
43+
// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ef 55 af 05 <unknown>
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46+
trn2 p15.h, p15.h, p15.h
47+
// CHECK-INST: trn2 p15.h, p15.h, p15.h
48+
// CHECK-ENCODING: [0xef,0x55,0x6f,0x05]
49+
// CHECK-ERROR: instruction requires: sve
50+
// CHECK-UNKNOWN: ef 55 6f 05 <unknown>
51+
52+
trn2 p15.d, p15.d, p15.d
53+
// CHECK-INST: trn2 p15.d, p15.d, p15.d
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// CHECK-ENCODING: [0xef,0x55,0xef,0x05]
55+
// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ef 55 ef 05 <unknown>

‎test/MC/AArch64/SVE/uzp1-diagnostics.s‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
2+
3+
// Invalid element kind.
4+
uzp1 z10.h, z22.h, z31.x
5+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
6+
// CHECK-NEXT: uzp1 z10.h, z22.h, z31.x
7+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8+
9+
// Element size specifiers should match.
10+
uzp1 z10.h, z3.h, z15.b
11+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
12+
// CHECK-NEXT: uzp1 z10.h, z3.h, z15.b
13+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
14+
15+
// Too few operands
16+
uzp1 z1.h, z2.h
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
18+
// CHECK-NEXT: uzp1 z1.h, z2.h
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
// z32 is not a valid SVE data register
22+
uzp1 z1.s, z2.s, z32.s
23+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
24+
// CHECK-NEXT: uzp1 z1.s, z2.s, z32.s
25+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26+
27+
// p16 is not a valid SVE predicate register
28+
uzp1 p1.s, p2.s, p16.s
29+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30+
// CHECK-NEXT: uzp1 p1.s, p2.s, p16.s
31+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32+
33+
// Combining data and predicate registers as operands
34+
uzp1 z1.s, z2.s, p3.s
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
36+
// CHECK-NEXT: uzp1 z1.s, z2.s, p3.s
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38+
39+
// Combining predicate and data registers as operands
40+
uzp1 p1.s, p2.s, z3.s
41+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
42+
// CHECK-NEXT: uzp1 p1.s, p2.s, z3.s
43+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎test/MC/AArch64/SVE/uzp1.s‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
6+
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
10+
uzp1 z31.b, z31.b, z31.b
11+
// CHECK-INST: uzp1 z31.b, z31.b, z31.b
12+
// CHECK-ENCODING: [0xff,0x6b,0x3f,0x05]
13+
// CHECK-ERROR: instruction requires: sve
14+
// CHECK-UNKNOWN: ff 6b 3f 05 <unknown>
15+
16+
uzp1 z31.h, z31.h, z31.h
17+
// CHECK-INST: uzp1 z31.h, z31.h, z31.h
18+
// CHECK-ENCODING: [0xff,0x6b,0x7f,0x05]
19+
// CHECK-ERROR: instruction requires: sve
20+
// CHECK-UNKNOWN: ff 6b 7f 05 <unknown>
21+
22+
uzp1 z31.s, z31.s, z31.s
23+
// CHECK-INST: uzp1 z31.s, z31.s, z31.s
24+
// CHECK-ENCODING: [0xff,0x6b,0xbf,0x05]
25+
// CHECK-ERROR: instruction requires: sve
26+
// CHECK-UNKNOWN: ff 6b bf 05 <unknown>
27+
28+
uzp1 z31.d, z31.d, z31.d
29+
// CHECK-INST: uzp1 z31.d, z31.d, z31.d
30+
// CHECK-ENCODING: [0xff,0x6b,0xff,0x05]
31+
// CHECK-ERROR: instruction requires: sve
32+
// CHECK-UNKNOWN: ff 6b ff 05 <unknown>
33+
34+
uzp1 p15.b, p15.b, p15.b
35+
// CHECK-INST: uzp1 p15.b, p15.b, p15.b
36+
// CHECK-ENCODING: [0xef,0x49,0x2f,0x05]
37+
// CHECK-ERROR: instruction requires: sve
38+
// CHECK-UNKNOWN: ef 49 2f 05 <unknown>
39+
40+
uzp1 p15.s, p15.s, p15.s
41+
// CHECK-INST: uzp1 p15.s, p15.s, p15.s
42+
// CHECK-ENCODING: [0xef,0x49,0xaf,0x05]
43+
// CHECK-ERROR: instruction requires: sve
44+
// CHECK-UNKNOWN: ef 49 af 05 <unknown>
45+
46+
uzp1 p15.h, p15.h, p15.h
47+
// CHECK-INST: uzp1 p15.h, p15.h, p15.h
48+
// CHECK-ENCODING: [0xef,0x49,0x6f,0x05]
49+
// CHECK-ERROR: instruction requires: sve
50+
// CHECK-UNKNOWN: ef 49 6f 05 <unknown>
51+
52+
uzp1 p15.d, p15.d, p15.d
53+
// CHECK-INST: uzp1 p15.d, p15.d, p15.d
54+
// CHECK-ENCODING: [0xef,0x49,0xef,0x05]
55+
// CHECK-ERROR: instruction requires: sve
56+
// CHECK-UNKNOWN: ef 49 ef 05 <unknown>

‎test/MC/AArch64/SVE/uzp2-diagnostics.s‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
2+
3+
// Invalid element kind.
4+
uzp2 z6.h, z23.h, z31.x
5+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
6+
// CHECK-NEXT: uzp2 z6.h, z23.h, z31.x
7+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8+
9+
// Element size specifiers should match.
10+
uzp2 z0.h, z30.h, z24.b
11+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
12+
// CHECK-NEXT: uzp2 z0.h, z30.h, z24.b
13+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
14+
15+
// Too few operands
16+
uzp2 z1.h, z2.h
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
18+
// CHECK-NEXT: uzp2 z1.h, z2.h
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
// z32 is not a valid SVE data register
22+
uzp2 z1.s, z2.s, z32.s
23+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
24+
// CHECK-NEXT: uzp2 z1.s, z2.s, z32.s
25+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26+
27+
// p16 is not a valid SVE predicate register
28+
uzp2 p1.s, p2.s, p16.s
29+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30+
// CHECK-NEXT: uzp2 p1.s, p2.s, p16.s
31+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32+
33+
// Combining data and predicate registers as operands
34+
uzp2 z1.s, z2.s, p3.s
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
36+
// CHECK-NEXT: uzp2 z1.s, z2.s, p3.s
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38+
39+
// Combining predicate and data registers as operands
40+
uzp2 p1.s, p2.s, z3.s
41+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
42+
// CHECK-NEXT: uzp2 p1.s, p2.s, z3.s
43+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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