Add boot_argument(), returns the value an a* register had at boot time

asm.S

@@ -1,8 +1,10 @@
 #if __riscv_xlen == 64
+# define XLEN_WORD .8byte
 # define STORE    sd
 # define LOAD     ld
 # define LOG_REGBYTES 3
 #else
+# define XLEN_WORD .4byte
 # define STORE    sw
 # define LOAD     lw
 # define LOG_REGBYTES 2
@@ -46,6 +48,17 @@ _abs_start:
     .cfi_startproc
     .cfi_undefined ra
 
+    la t0, boot_args
+    STORE a0, 0*REGBYTES(t0)
+    STORE a1, 1*REGBYTES(t0)
+    STORE a2, 2*REGBYTES(t0)
+    STORE a3, 3*REGBYTES(t0)
+    STORE a4, 4*REGBYTES(t0)
+    STORE a5, 5*REGBYTES(t0)
+    STORE a6, 6*REGBYTES(t0)
+    STORE a7, 7*REGBYTES(t0)
+    fence rw, rw
+
     csrw mie, 0
     csrw mip, 0
 
@@ -117,6 +130,21 @@ _abs_start:
 
     .cfi_endproc
 
+/*
+    Space to save the value of argument registers at boot
+*/
+.section .data
+.global boot_args
+boot_args:
+    XLEN_WORD 0 // a0
+    XLEN_WORD 0 // a1
+    XLEN_WORD 0 // a2
+    XLEN_WORD 0 // a3
+    XLEN_WORD 0 // a4
+    XLEN_WORD 0 // a5
+    XLEN_WORD 0 // a6
+    XLEN_WORD 0 // a7
+
 /*
     Trap entry point (_start_trap)
 

src/lib.rs

@@ -353,8 +353,13 @@ extern "C" {
 
     // Initial values of the .data section (stored in Flash)
     static _sidata: u32;
+
+    static boot_args: [usize; ARGUMENT_REGISTERS_COUNT];
 }
 
+/// a0 to a7
+const ARGUMENT_REGISTERS_COUNT: usize = 8;
+
 /// Rust entry point (_start_rust)
 ///
 /// Zeros bss section, initializes data section and calls main. This function
@@ -389,6 +394,14 @@ pub unsafe extern "C" fn start_rust() -> ! {
     main();
 }
 
+/// Returns the value an argument register had when this firmware was first booted.
+///
+/// Some of these registers may have values passed by the previous boot stage:
+/// <https://doc.coreboot.org/arch/riscv/index.html#stage-handoff-protocol>
+pub fn boot_argument(index: usize) -> Option<usize> {
+    unsafe { boot_args.get(index).copied() }
+}
+
 /// Registers saved in trap handler
 #[allow(missing_docs)]
 #[repr(C)]