Create aarch32-cpu and aarch32-rt crates. #78
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This got big, and Armv5TE stuff is broken in weird ways, so I'm going to pull out parts of this as separate PRs. Current list of weirdness:
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Needs to be rebased. I can also perform some testing on the Zynq7000 |
Replaces cortex-r-rt, cortex-a-rt and cortex-ar.
) Bigger stacks, so the examples work in release mode ) Formatting ) Remove gic feature
They have no atomics to switch tests to use portable-atomic. Also give the examples more stack space to match mps3-an536 tests. IFAR is also not available, so skip it in the prefetch abort test.
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Phew, all tests pass on ARMv4T (PXA25) and ARMv5TE (ARM926) in QEMU. |
robamu
reviewed
Oct 27, 2025
robamu
reviewed
Oct 27, 2025
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I tested some of the Zynq7000 examples, and they work without issues :) Those did not include floating code I think. Might add that to test the double precision support. |
The old cortex-a-rt library supported interrupt context saving for FPUs with 32 double-precision registers and that was lost in the merge. This brings it back, but calls the feature `fpu-d32` to reflect what it does. Also tests with this feature enabled.
robamu
reviewed
Oct 28, 2025
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Found one more little thing. Otherwise LGTM (I might test this soon on a SAM9G20 as well, let's see whether I can find some time..) Incredible work! |
robamu
approved these changes
Oct 29, 2025
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Replaces cortex-r-rt, cortex-a-rt and cortex-ar.