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Commit 3179602

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jgvillyjgvilly
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Semiworking AES, needs final validation.
1 parent 1567bdb commit 3179602

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4 files changed

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‎aesTest/testprogram.dat

+75-61
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@@ -1,27 +1,56 @@
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20080401
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40806000
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20180006
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adac0000
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00000000
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@@ -32,49 +61,20 @@ adac0000
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488b4000
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00000000
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08000024
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00000000
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00021140
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00021200
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00000000
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00000000
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00000000
@@ -94,16 +94,30 @@ adac0000
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00000000
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00000000
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00000000
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8c100000
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ac107000
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ac107000
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ac107000
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02048824
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14110005
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00108042
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08000043
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8c1a0000
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ac1a7000
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ac1a7000
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ac1a7000
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08000067
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14170003
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20170001
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488e0000
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08000079
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0000b820
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48980000
109-
08000024
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40956000
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08000043

‎mips_top.v

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,15 @@
11
module mips_top
22
(input clk, serialClk, rst, [3:0] INT, output serial, output [31:0] pc_current, instr, dmem_addr, dmem_out, rd_dm);
33
//wire [31:0] instr, alu_out, wd_dm, rd_dm;
4-
wire dmem_we;
4+
wire dmem_we, Empty_out;
55
//mips MIPS (.clk(clk), .rst(rst), .instr(instr), .rd_dm(rd_dm), .we_dm(we_dm), .pc_current(pc_current), .alu_out(alu_out), .wd_dm(wd_dm), .INT(INT));
6-
mips MIPS (.clk(clk), .rst(rst), .instr(instr), .rd_dm(rd_dm), .dmem_we(dmem_we), .pc_current(pc_current), .dmem_addr(dmem_addr), .dmem_out(dmem_out), .INT(INT));
6+
mips MIPS (.clk(clk), .rst(rst), .instr(instr), .rd_dm(rd_dm), .dmem_we(dmem_we), .pc_current(pc_current), .dmem_addr(dmem_addr), .dmem_out(dmem_out), .INT({INT[3:1], Empty_out}));
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//imem #(32)IMEM (.a(pc_current[7:2]), .y(instr));
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imem #(32)IMEM (.a(pc_current), .y(instr));
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//dmem #(32)DMEM (.clk(clk), .we(we_dm), .a(alu_out), .d(wd_dm), .q(rd_dm));
1010
dmem #(32)DMEM (.clk(clk), .we(dmem_we), .a(dmem_addr), .d(dmem_out), .q(rd_dm));
1111

12-
uart_top UART (.clk(clk), .RClk(serialClk), .reset(rst), .we(dmem_we), .dataIn(dmem_out), .address(dmem_addr), .serial(serial));
12+
uart_top UART (.clk(clk), .RClk(serialClk), .reset(rst), .we(dmem_we), .dataIn(dmem_out), .address(dmem_addr), .serial(serial), .Empty_out(Empty_out));
1313

1414
//mips MIPS (.clk(clk_5KHz), .rst(rst), .instr(instr), .rd_dm(rd_dm), .we_dm(we_dm), .pc_current(pc_current), .alu_out(alu_out), .wd_dm(wd_dm));
1515
//dmem #(32)DMEM (.clk(clk_5KHz), .we(we_dm), .a(alu_out[5:0]), .d(wd_dm), .q(rd_dm));

‎parts.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ endmodule
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9797
module dmem #(parameter wide = 8)
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(input clk, we, [31:0] a, [wide-1:0] d, output [wide-1:0] q);
99-
reg [wide-1:0] ram [0:50];
99+
reg [wide-1:0] ram [0:500];
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//reg [wide-1:0] ram [0:91000];
101101
always @ (posedge clk) if (we & (a != 32'h0000_7000)) ram[a/4] <= d;
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assign q = ram[a/4];

‎uart/uart_top.v

+4-4
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
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`timescale 1ns/1ps
2-
module uart_top(input RClk, input clk, input reset, input we, input [31:0] dataIn, address, output serial);
2+
module uart_top(input RClk, input clk, input reset, input we, input [31:0] dataIn, address, output serial, Empty_out);
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wire write = ((we == 1'b1) && (address == 32'h0000_7000)) ? 1:0;
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wire [31:0] toUart;
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wire busy;
7-
wire Empty_out;
7+
//wire Empty_out;
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wire pNextWordToRead;
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reg [2:0] counter;
1010
wire [7:0] data;
@@ -64,7 +64,7 @@ endmodule
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6565
module aFifo
6666
#(parameter DATA_WIDTH = 32,
67-
ADDRESS_WIDTH = 5,
67+
ADDRESS_WIDTH = 6,
6868
FIFO_DEPTH = (1 << ADDRESS_WIDTH))
6969
//Reading port
7070
(//output reg [DATA_WIDTH-1:0] Data_out,
@@ -169,7 +169,7 @@ endmodule
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170170

171171
module GrayCounter
172-
#(parameter COUNTER_WIDTH = 5)
172+
#(parameter COUNTER_WIDTH = 6)
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174174
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
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