Automate architecture synchronization with latest LLVM #5
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* riscv: Fix printAliasInstr We do not want to append the entire string, only the single non-argument character. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> * riscv: Implement printCSRSystemRegister While upstream LLVM probably has a tablegen thing for these somewhere, the current import doesn't include them. Take the list from riscv-privileged-v1.10.pdf. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Fix a few registry access mode mappings * Fix rollback of operand access changes Re-fix operand access of three mov instructions * Remove binding breaking #if 0 The python script for generating constants in the bindings does not know how to handle the #if 0 statements included in these files. * Updated registry access on cmov instructions Registry access for the destination operand of the conditional move (cmov) opcodes were incorrectly listed as READ | WRITE. Although you would expect the two operands to be compared in this opcode, it instead relies on the associated flag in EFLAGS regardless of the value in the destination operand.
… etc. (capstone-engine#1725) * Fix a few registry access mode mappings * Fix rollback of operand access changes Re-fix operand access of three mov instructions * Remove binding breaking #if 0 The python script for generating constants in the bindings does not know how to handle the #if 0 statements included in these files. * Add files via upload Update registry access mode for several versions of pop such as POPDS, POPSS, etc
* fix bug in displacement offset * fix k0-k7 registers in X86 table.
…e-engine#1702) * mos65xx: use imm field for immediate operand value using the wrong field works on little-endian hosts, but on big-endian the wrong value would be read * mos65xx: set operand mem field to address also in relative modes previously the last operand would have an offset, which doesn't match the printed operand * mos65xx: add bpl instruction to test this demonstrates an address operand with relative addressing
…ieri/moffset_disp Fix the displacement offset for moffset-encoded operands
fixed library extension to build properly under CYGWIN
Correcting X86 Imm Size
support disassembling bytes from memoryview
…eg_access_fix2 Fix cmp register access on aarch64
…657-next Revert "Correcting X86 Imm Size"
add CI Test support
fix eflags effects for adc/sbb
Add ci_test steps && Fixed suite test for python3
MIPS Mapper Integration unify format style, closes rizinorg#2 Restored readme.md location ARM Arch & Synctools Usage Docs fix redundant header auto sync MIPS integration apply clang-format ignore .idea folder apply `black` reformat
SystemZ & XCore & Sparc & RISCV & PPC
Sparc PPC XCore SystemZ RISCV Instructions Printing & Mapping AArch64&Rizin disasm passing (with some target-specific generated table still needed - left unchecked for now) ARM&Rizin disasm passing Mips&Rizin disasm passing
Update generated files to match newest generator Invocation simplification, w.r.t. rizinorg#5 Turn on the build target
Resolve ARM Thumb decoding issue
Inst Printer Predicate fix architecture integrity check & ppc naming patch fixes mips naming & addressing issues
Cleanups & warning elimination
Finalizes problems on tests
Minor syncing README updates
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What is Auto-Sync ?
Capstone Auto-Sync is an initiative to partly automate the synchronization of certain architectures to the latest.
Most of the Capstone's
.incfiles a generated from LLVM's TableGen backend and processed by python scrips insuite/synctoolsinto C-compatible files, which leads to the problem that with LLVM's update, it's not always (hardly, in fact) possible to use the synctools without patch in regard to LLVM's upstream change.This syncing tools, however, using a custom-made LLVM TableGen backend (here) to generate
.incfiles natively usable by Capstone. With certain adaptations in Capstone's structure, it is possible to consistently automate large parts of the work on keeping up with LLVM's latest Target (i.e..tdfiles) update, and optimally, there could be zero-overhead in the process of updating(see this patch on missing bcxf instructions)https://github.com/Phosphorus15/Capstone/blob/1bca4211bd7c132c57d0006a26de57d42a4bcdb9/sync/SYNCING.md?plain=1#L1-L17
What is done in this PR?
In this PR, we adapted following architectures with the Auto-Sync structure base on the
nextbranch, and made sure they pass the test suite given by Capstone, and also by the analysis tools rizin (which also uses Capstone):What is yet to be done?
Capstone's instructions mapping info (like enums) exposed to various bindings (Python bindings, etc.) are not affected by Auto-Sync procedure, and so have to be manually edited if anything like new instructions/operands type was added by LLVM.