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Hypervisor extension#612

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defermelowie wants to merge 28 commits intoriscv:masterriscv/sail-riscv:masterfrom defermelowie:ext_hypervisor_cleanupdefermelowie/riscv-hext-sail:ext_hypervisor_cleanupCopy head branch name to clipboard

+2,471-557

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Commits on Oct 21, 2024

• Setup for hypervisor extension

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• Add hypervisor extension state

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• Add read/write for hypervisor extension CSRs

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• Add emulator flag to enable hypervisor extension on boot

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• Add privilege level switches through xret/ecall

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• Fix pre-commit issues

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Commits on Oct 22, 2024

• Address translation failures provide ExceptionContext

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• Hypervisor CSRs should be accessable from HS-mode

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• Implemented banking of supervisor CSRs in virtualized modes

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• Add promotion of illegal instruction exceptions to virtual instruction exceptions

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• Fix vsstatus XLEN mismatch

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• Fix missing interrupt types

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Commits on Oct 23, 2024

• Add hypervisor guest address translation & protection register

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• Add delegation of interrupt to VS-mode

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• Define hypervisor fence instructions

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• Update WFI semantics

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Commits on Oct 28, 2024

• Add parameters of G-stage address translation modes

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Commits on Oct 31, 2024

• Add getters for fields of HGATP

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• Model implicit page walk errors

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• Add initial 'second level address translation' implementation

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• Use seperate TLB for each address translation stage

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• Fix update of A/D bits for VS-level pages

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• Fix typecheck error when xlen == 32

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• Report transformed instructions upon memory exceptions

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• Add hypervisor load & store instructions

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• Refactor TODOs and comments

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• Refactor G-stage exception converter into PTW_error to exception converter fn

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Commits on Nov 7, 2024

• Various small fixes after manual inspection of third-party tests

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