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Refactor chip reset #597
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Refactor chip reset #597
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ext_init should remain (possibly renamed). Our sail-cheri-riscv uses it so this would block us updating if we need to keep it going. But, more importantly, we shouldn't delete hooks just because one possible user isn't using them. Any hook that has a real use case is supposed to be there, it's just the only use case so far is sail-cheri-riscv and thus the hooks that exist are the ones that it needed. |
Also, the latter is very much used: and still used (renamed) in the model for the proposed standard version: |
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ext_(rvfi_)init should stay as ext_(rvfi_)reset
They should be initialised for RVFI though. |
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Ah yes you're quite right about the
Yeah I'm not exactly sure what the story is on these ext_ hooks and what happens to the CHERI repos. It seems like it's making good progress towards ratification and then it would make sense for it to just be directly in the model. We probably still want to keep its code out of the way of people who don't care about CHERI I guess though. Do you know of anyone else using these hooks? Could we discuss it in the CHERI Tech chat on Thursday?
The generated C code still initialises them to 0 when the model is initialised by Currently there isn't really an interface to do that, but we do it internally via our lock-step verif system. When the real DUT gets reset, we reset the Sail model by calling |
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@Timmmm I still see the |
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Oops totally forgot about that. I've added |
Not sure why but ci is unhappy:
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Oops I forgot about RVFI. Should pass now. |
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Overall this looks good, but as far as I can tell this will break the RVFI support. It should reset registers to all zero so you have a reproducible starting point for divergence testing.
I'm pretty sure that reset is done automatically by |
Ah yes it does call model_init in the rvfi loop. Does this re-run all sail global initializers? If so then please ignore my comment. LGTM. |
Yep it calls
|
This simplifies, clarifies and fixes the reset functionality. Until now the model conflates reset and initialisation, and does way more than it should on reset. The RISC-V spec only requires a very small number of things to be reset. This change: 1. Renames the `init` functions to `reset`, to clarify that they correspond to resetting the chip. 2. Removes the `ext_init` and `ext_rvfi_init` functions. The latter is not used and the former is only used by the old CHERI code. 2. Removes the reset of the X and F registers. These are non-reset. 3. Removes the reset of various CSRs that are non-reset (`mip`, `mie`, `mideleg`, `mtvec`, `mepc`, etc). 4. Adds reset of `mstatus[MIE]` and `mstatus[MPRV]`. As far as I can see they were missing. 5. Add one-time init of `mhartid` etc to 0. I didn't remove the vector register resets yet. That needs a bigger refactor. Also note that currently there is no way to actually do a chip reset mid-simulation, but that will be needed eventually.
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This simplifies, clarifies and fixes the reset functionality.
Until now the model conflates reset and initialisation, and does way more than it should on reset. The RISC-V spec only requires a very small number of things to be reset.
This change:
init
functions toreset
, to clarify that they correspond to resetting the chip.ext_init
andext_rvfi_init
functions. The latter is not used and the former is only used by the old CHERI code.mip
,mie
,mideleg
,mtvec
,mepc
, etc).mstatus[MIE]
andmstatus[MPRV]
. As far as I can see they were missing.mhartid
etc to 0.I didn't remove the vector register resets yet. That needs a bigger refactor.
Also note that currently there is no way to actually do a chip reset mid-simulation, but that will be needed eventually.