Merge pull request #897 from riscv/priority

AR: Update priority table from latest privspec
riscv · Oct 6, 2023 · 79e257b · 79e257b
2 parents 9f44898 + aaab8fb
commit 79e257b
Showing 1 changed file with 19 additions and 19 deletions.
diff --git a/Sdtrig.tex b/Sdtrig.tex
@@ -114,36 +114,36 @@ \section{Priority}
 
 \begin{table}[H]
 \centering
-\begin{tabular}{|l|r|l|l|}
+\begin{tabulary}{\textwidth}{|l|p{.7in}|p{2.3in}|p{2.5in}|}
   \hline
-  Priority      & Exception & Description & Trigger \\
-                &      Code &             & \\
+  Priority      & Exception Code & Description & Trigger \\
   \hline
   {\em Highest} &          3 & & etrigger \\
                 &          3 & & icount \\
                 &          3 & & itrigger \\
-                &          3 & & mcontrol/mcontrol6 after \\
-                &            & & \hspace{2em}(on previous instruction) \\
+                &          3 & & mcontrol/mcontrol6 after (on previous instruction) \\
                 \hline
                 &          3 & Instruction address breakpoint & mcontrol/mcontrol6 execute address before \\ \hline
-                &         12 & Instruction page fault & \\ \hline
-                &          1 & Instruction access fault & \\ \hline
+                &  12, 20, 1 & During instruction address translation:
+                                First encountered page fault, guest-page fault, or access fault & \\ \hline
+                &          1 & With physical address for instruction:
+                                Instruction access fault & \\ \hline
                 &          3 & & mcontrol/mcontrol6 execute data before \\ \hline
                 &          2 & Illegal instruction & \\
+                &         22 & Virtual instruction & \\
                 &          0 & Instruction address misaligned & \\
-                &   8, 9, 11 & Environment call & \\
+                & 8, 9, 10, 11 & Environment call & \\
                 &          3 & Environment break & \\
-                &          3 & Load/Store/AMO address breakpoint & mcontrol/mcontrol6 load/store address before \\
-                &          3 & & mcontrol/mcontrol6 store data before \\ \hline
-                &          6 & Store/AMO address misaligned & \\
-                &          4 & Load address misaligned & \\ \hline
-                &         15 & Store/AMO page fault & \\
-                &         13 & Load page fault & \\ \hline
-                &          7 & Store/AMO access fault & \\
-                &          5 & Load access fault & \\
-  {\em Lowest}  &          3 & & mcontrol/mcontrol6 load data before \\
-  \hline
-\end{tabular}
+                &          3 & Load/Store/AMO address breakpoint & mcontrol/mcontrol6 load/store address/data before \\ \hline
+                &       4, 6 & Optionally: Load/Store/AMO address misaligned & \\ \hline
+                & 13, 15, 21, 23, 5, 7 & During address translation for an explicit memory access:
+                                    First encountered page fault, guest-page fault, or access fault & \\ \hline
+                & 5, 7       & With physical address for an explicit memory access:
+                                Load/store/AMO access fault & \\ \hline
+                & 4, 6       & If not higher priority:
+                                Load/store/AMO address misaligned & \\ \hline
+  {\em Lowest}  &          3 & & mcontrol/mcontrol6 load data before \\ \hline
+\end{tabulary}
 \caption{Synchronous exception priority in decreasing priority order.}
 \label{tab:priority}
 \end{table}