[LLVM][XTHeadVector] Implement intrinsics for vdiv/vdivu/vrem/vremu. (l…

…lvm#64)

* [LLVM][XTHeadVector] Define intrinsic functions for vdiv/vrem.

* [LLVM][XTHeadVector] Define pseudos and pats for vdiv/vrem.

* [LLVM][XTHeadVector] Add test cases.

* [NFC][XTHeadVector] Update README.

README.md

@@ -46,6 +46,7 @@ Any feature not listed below but present in the specification should be consider
     - (Done) `12.6. Vector Narrowing Integer Right Shift Instructions`
     - (Done) `12.7 Vector Integer Comparison Instructions`
     - (Done) `12.8. Vector Integer Min/Max Instructions`
+    - (Done) `12.10. Vector Integer Divide Instructions`
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:
   - (WIP) `6. Configuration-Setting and Utility`
     - (Done) `6.1. Set vl and vtype`

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -687,6 +687,12 @@ let TargetPrefix = "riscv" in {
   defm th_vmin : XVBinaryAAX;
   defm th_vmaxu : XVBinaryAAX;
   defm th_vmax : XVBinaryAAX;
+
+  // 12.10 Vector Integer Divide Instructions
+  defm th_vdivu : XVBinaryAAX;
+  defm th_vdiv : XVBinaryAAX;
+  defm th_vremu : XVBinaryAAX;
+  defm th_vrem : XVBinaryAAX;
 } // TargetPrefix = "riscv"
 
 let TargetPrefix = "riscv" in {

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -1928,6 +1928,24 @@ multiclass XVPseudoVMSGE_VX_VI {
   }
 }
 
+multiclass XVPseudoVDIV_VV_VX {
+  foreach m = MxListXTHeadV in {
+    defvar mx = m.MX;
+    defvar sews = SchedSEWSet<mx>.val;
+    foreach e = sews in {
+      defvar WriteVIDivV_MX_E = !cast<SchedWrite>("WriteVIDivV_" # mx # "_E" # e);
+      defvar WriteVIDivX_MX_E = !cast<SchedWrite>("WriteVIDivX_" # mx # "_E" # e);
+      defvar ReadVIDivV_MX_E = !cast<SchedRead>("ReadVIDivV_" # mx # "_E" # e);
+      defvar ReadVIDivX_MX_E = !cast<SchedRead>("ReadVIDivX_" # mx # "_E" # e);
+
+      defm "" : XVPseudoBinaryV_VV<m, "", e>,
+                Sched<[WriteVIDivV_MX_E, ReadVIDivV_MX_E, ReadVIDivV_MX_E, ReadVMask]>;
+      defm "" : XVPseudoBinaryV_VX<m, "", e>,
+                Sched<[WriteVIDivX_MX_E, ReadVIDivV_MX_E, ReadVIDivX_MX_E, ReadVMask]>;
+    }
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Helpers to define the intrinsic patterns for the XTHeadVector extension.
 //===----------------------------------------------------------------------===//
@@ -2609,6 +2627,23 @@ let Predicates = [HasVendorXTHeadV] in {
   defm : XVPatBinaryV_VV_VX<"int_riscv_th_vmax", "PseudoTH_VMAX", AllIntegerXVectors>;
 }
 
+//===----------------------------------------------------------------------===//
+// 12.10. Vector Integer Divide Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXTHeadV] in {
+  defm PseudoTH_VDIVU : XVPseudoVDIV_VV_VX;
+  defm PseudoTH_VDIV  : XVPseudoVDIV_VV_VX;
+  defm PseudoTH_VREMU : XVPseudoVDIV_VV_VX;
+  defm PseudoTH_VREM  : XVPseudoVDIV_VV_VX;
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vdivu", "PseudoTH_VDIVU", AllIntegerXVectors, isSEWAware=1>;
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vdiv", "PseudoTH_VDIV", AllIntegerXVectors, isSEWAware=1>;
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vremu", "PseudoTH_VREMU", AllIntegerXVectors, isSEWAware=1>;
+  defm : XVPatBinaryV_VV_VX<"int_riscv_th_vrem", "PseudoTH_VREM", AllIntegerXVectors, isSEWAware=1>;
+} // Predicates = [HasVendorXTHeadV]
+
 //===----------------------------------------------------------------------===//
 // 12.14. Vector Integer Merge and Move Instructions
 //===----------------------------------------------------------------------===//