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Merged
merged 25 commits into from
Jan 11, 2020
Merged

Inline operators #822

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0bee5d8
WIP inline operators
leonardt Dec 2, 2019
c27f8c0
Merge branch 'master' into inline-operators
leonardt Dec 5, 2019
6a01272
Define operator ASTs
leonardt Dec 6, 2019
bcc96a9
inline basic primitives
leonardt Dec 13, 2019
b49ad83
Add missing files
leonardt Dec 13, 2019
c177306
link verilogAST in tests
leonardt Dec 13, 2019
ec4fedc
Link verilogAST
leonardt Dec 13, 2019
3f29c95
Update std
leonardt Dec 14, 2019
4dc9af0
Add assign inlining logic
leonardt Dec 18, 2019
c53bedb
Checkout verilogast branch
leonardt Dec 18, 2019
43d0ca9
Merge branch 'master' into inline-operators
leonardt Dec 18, 2019
0b0ef88
Guard inlining logic
leonardt Dec 18, 2019
9b5a118
Inline outputs
leonardt Dec 19, 2019
a6a7439
Rename Primitive -> VerilogPrimitive
leonardt Jan 6, 2020
1e4ac83
Fix boolean literal codegen
leonardt Jan 6, 2020
503878d
Merge branch 'master' into inline-operators
rdaly525 Jan 6, 2020
317aadd
Use master verilogAST
leonardt Jan 6, 2020
50aac95
Inline binary reduce ops
leonardt Jan 6, 2020
03e65d2
Merge branch 'master' into inline-operators
leonardt Jan 6, 2020
10253f1
Add mux inline logic/test
leonardt Jan 6, 2020
123c1c4
Inline muxes
leonardt Jan 7, 2020
e8b24ec
Inline unary reduce
leonardt Jan 7, 2020
f09387a
Merge branch 'master' into inline-operators
leonardt Jan 11, 2020
838dbd6
Support inline verilog node
leonardt Jan 11, 2020
c7735b7
Revert to master
leonardt Jan 11, 2020
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2 changes: 1 addition & 1 deletion CMakeLists.txt
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Expand Up @@ -72,5 +72,5 @@ add_subdirectory(${CMAKE_CURRENT_BINARY_DIR}/googletest-src
include_directories(${CMAKE_SOURCE_DIR}/include)
enable_testing()
add_executable(test_verilog tests/gtest/test_verilog.cpp)
target_link_libraries(test_verilog gtest_main coreir)
target_link_libraries(test_verilog gtest_main coreir coreir-commonlib)
add_test(NAME test_verilog COMMAND test_verilog WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests/gtest)
254 changes: 215 additions & 39 deletions include/coreir/definitions/coreVerilog.hpp
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@@ -1,55 +1,229 @@
#include "verilogAST.hpp"

namespace vAST = verilogAST;

std::vector<std::unique_ptr<vAST::Expression>>
make_args(std::vector<std::string> args) {
std::vector<std::unique_ptr<vAST::Expression>> arg_ptrs;
for (auto a : args) {
arg_ptrs.push_back(vAST::make_id(a));
}
return arg_ptrs;
}

std::vector<std::unique_ptr<vAST::Expression>>
make_ext_args(std::vector<std::unique_ptr<vAST::Expression>> args) {
return args;
}

std::unique_ptr<vAST::CallExpr> make_signed_call(const char *id) {
std::vector<std::unique_ptr<vAST::Expression>> args;
args.push_back(vAST::make_id(std::string(id)));
return std::make_unique<vAST::CallExpr>("$signed", std::move(args));
}

using namespace CoreIR;
using namespace std;
void CoreIRLoadVerilog_coreir(Context* c) {
std::map<std::string,std::map<std::string,std::string>> coreVMap({
std::map<std::string,std::map<std::string,std::pair<std::string,std::function<std::unique_ptr<vAST::Expression>()>>>>
coreVMap({
{"unary",{
{"wire","in"},
{"not","~in"},
{"neg","-in"}
{"wire",{
"in",
[]() {return vAST::make_id("in");}
}},
{"not",{
"~in",
[]() {return std::make_unique<vAST::UnaryOp>(vAST::make_id("in"), vAST::UnOp::INVERT);}
}},
{"neg",{
"-in",
[]() {return std::make_unique<vAST::UnaryOp>(vAST::make_id("in"), vAST::UnOp::MINUS);}
}}
}},
{"unaryReduce",{
{"andr","&in"},
{"orr","|in"},
{"xorr","^in"}
{"andr",{"&in",
[]() {return std::make_unique<vAST::UnaryOp>(vAST::make_id("in"), vAST::UnOp::AND);}
}},
{"orr",{"|in",
[]() {return std::make_unique<vAST::UnaryOp>(vAST::make_id("in"), vAST::UnOp::OR);}
}},
{"xorr",{"^in",
[]() {return std::make_unique<vAST::UnaryOp>(vAST::make_id("in"), vAST::UnOp::XOR);}
}}
}},
{"binary",{
{"and","in0 & in1"},
{"or","in0 | in1"},
{"xor","in0 ^ in1"},
{"shl","in0 << in1"},
{"lshr","in0 >> in1"},
{"ashr","$signed(in0) >>> in1"},
{"add","in0 + in1"},
{"sub","in0 - in1"},
{"mul","in0 * in1"},
{"udiv","in0 / in1"},
{"sdiv","$signed(in0) / $signed(in1)"}
{"and",{"in0 & in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::AND, vAST::make_id("in1"));
}}},
{"or",{"in0 | in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::OR, vAST::make_id("in1"));
}}},
{"xor",{"in0 ^ in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::XOR, vAST::make_id("in1"));
}}},
{"shl",{"in0 << in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::LSHIFT, vAST::make_id("in1"));
}}},
{"lshr",{"in0 >> in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::RSHIFT, vAST::make_id("in1"));
}}},
{"ashr",{"$signed(in0) >>> in1",
[]() {return std::make_unique<vAST::BinaryOp>(make_signed_call("in0"),
vAST::BinOp::ARSHIFT, vAST::make_id("in1"));
}}},
{"add",{"in0 + in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::ADD, vAST::make_id("in1"));
}}},
{"sub",{"in0 - in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::SUB, vAST::make_id("in1"));
}}},
{"mul",{"in0 * in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::MUL, vAST::make_id("in1"));
}}},
{"udiv",{"in0 / in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::DIV, vAST::make_id("in1"));
}}},
{"sdiv",{"$signed(in0) / $signed(in1)",
[]() {return std::make_unique<vAST::BinaryOp>(make_signed_call("in0"),
vAST::BinOp::DIV, make_signed_call("in1"));
}}}
}},
{"binaryReduce",{
{"eq","in0 == in1"},
{"neq","in0 != in1"},
{"slt","$signed(in0) < $signed(in1)"},
{"sgt","$signed(in0) > $signed(in1)"},
{"sle","$signed(in0) <= $signed(in1)"},
{"sge","$signed(in0) >= $signed(in1)"},
{"ult","in0 < in1"},
{"ugt","in0 > in1"},
{"ule","in0 <= in1"},
{"uge","in0 >= in1"}
{"eq",{"in0 == in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::EQ, vAST::make_id("in1"));
}}},
{"neq",{"in0 != in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::NEQ, vAST::make_id("in1"));
}}},
{"slt",{"$signed(in0) < $signed(in1)",
[]() {return std::make_unique<vAST::BinaryOp>(make_signed_call("in0"),
vAST::BinOp::LT, make_signed_call("in1"));
}}},
{"sgt",{"$signed(in0) > $signed(in1)",
[]() {return std::make_unique<vAST::BinaryOp>(make_signed_call("in0"),
vAST::BinOp::GT, make_signed_call("in1"));
}}},
{"sle",{"$signed(in0) <= $signed(in1)",
[]() {return std::make_unique<vAST::BinaryOp>(make_signed_call("in0"),
vAST::BinOp::LTE, make_signed_call("in1"));
}}},
{"sge",{"$signed(in0) >= $signed(in1)",
[]() {return std::make_unique<vAST::BinaryOp>(make_signed_call("in0"),
vAST::BinOp::GTE, make_signed_call("in1"));
}}},
{"ult",{"in0 < in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::LT, vAST::make_id("in1"));
}}},
{"ugt",{"in0 > in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::GT, vAST::make_id("in1"));
}}},
{"ule",{"in0 <= in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::LTE, vAST::make_id("in1"));
}}},
{"uge",{"in0 >= in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::GTE, vAST::make_id("in1"));
}}}
}},
{"other",{
{"mux","sel ? in1 : in0"},
{"slice","in[hi-1:lo]"},
{"concat","{in1,in0}"},
{"zext","{{(width_out-width_in){1'b0}},in}"},
{"sext","{{(width_out-width_in){in[width_in-1]}},in}"},
{"strip","in"},
{"wrap","in"},
{"const","value"},
{"tribuf","en ? in : 'hz"},
{"ibuf","in"},
{"mux",{"sel ? in1 : in0",
[](){ return std::make_unique<vAST::TernaryOp>(
vAST::make_id("sel"),
vAST::make_id("in1"),
vAST::make_id("in0"));
}}},
{"slice",{"in[hi-1:lo]",
[](){ return std::make_unique<vAST::Slice>(
vAST::make_id("in"),
vAST::make_binop(
vAST::make_id("hi"),
vAST::BinOp::SUB,
vAST::make_num("1")
),
vAST::make_id("lo"));
}}},
{"concat",{"{in1,in0}",
[](){ return std::make_unique<vAST::Concat>(make_args({"in1", "in0"}));
}}},
{"zext",{"{{(width_out-width_in){1'b0}},in}",
[](){
// Can't use initializer list of vector of unique ptrs, so we
// explicitly construct it
std::vector<std::unique_ptr<vAST::Expression>> zext_args;
zext_args.push_back(
std::make_unique<vAST::Replicate>(
vAST::make_binop(
vAST::make_id("width_out"),
vAST::BinOp::SUB,
vAST::make_id("width_in")
),
std::make_unique<vAST::NumericLiteral>("0", 1, false,
vAST::Radix::BINARY)
)
);
zext_args.push_back(
vAST::make_id("in")
);
return std::make_unique<vAST::Concat>(std::move(zext_args));
}}},
{"sext",{"{{(width_out-width_in){in[width_in-1]}},in}",
[](){
// Can't use initializer list of vector of unique ptrs, so we
// explicitly construct it
std::vector<std::unique_ptr<vAST::Expression>> sext_args;
sext_args.push_back(
std::make_unique<vAST::Replicate>(
vAST::make_binop(
vAST::make_id("width_out"),
vAST::BinOp::SUB,
vAST::make_id("width_in")
),
std::make_unique<vAST::Index>(
vAST::make_id("in"),
vAST::make_binop(
vAST::make_id("width_in"),
vAST::BinOp::SUB,
vAST::make_num("1")
)
)
)
);
sext_args.push_back(vAST::make_id("in"));
return std::make_unique<vAST::Concat>(std::move(sext_args));
}}},
{"strip",{"in",
[](){ return vAST::make_id("in");
}}},
{"wrap",{"in",
[](){ return vAST::make_id("in");
}}},
{"const",{"value",
[](){ return vAST::make_id("value");
}}},
{"tribuf",{"en ? in : 'hz",
[](){ return std::make_unique<vAST::TernaryOp>(
vAST::make_id("en"),
vAST::make_id("in"),
std::make_unique<vAST::NumericLiteral>("z", vAST::Radix::HEX));
}}},
{"ibuf",{"in",
[](){ return vAST::make_id("in");
}}}
//{"term",""}
//{"reg",""},
//{"mem",""},
Expand Down Expand Up @@ -143,7 +317,7 @@ void CoreIRLoadVerilog_coreir(Context* c) {
for (auto it0 : coreVMap) {
for (auto it1 : it0.second) {
string op = it1.first;
string vbody = it1.second;
string vbody = it1.second.first;
json vjson;
vjson["prefix"] = "coreir_";
vjson["definition"] = " assign out = " + vbody + ";";
Expand All @@ -156,7 +330,9 @@ void CoreIRLoadVerilog_coreir(Context* c) {
ASSERT(coreIMap.count(it1.first),"missing" + it1.first);
vjson["interface"] = coreIMap.at(it1.first);
}
vjson["primitive_type"] = it0.first;
core->getGenerator(op)->getMetaData()["verilog"] = vjson;
core->getGenerator(op)->setPrimitiveExpressionLambda(it1.second.second);
}
}

Expand Down
60 changes: 47 additions & 13 deletions include/coreir/definitions/corebitVerilog.hpp
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Expand Up @@ -3,23 +3,55 @@
using namespace CoreIR;
using namespace std;
void CoreIRLoadVerilog_corebit(Context* c) {
std::map<std::string,std::map<std::string,std::string>> bitVMap({
std::map<std::string,std::map<std::string,std::pair<std::string,std::function<std::unique_ptr<vAST::Expression>()>>>>
bitVMap({
{"unary",{
{"wire","in"},
{"not","~in"},
{"wire",{
"in",
[]() {return vAST::make_id("in");}
}},
{"not",{
"~in",
[]() {return std::make_unique<vAST::UnaryOp>(vAST::make_id("in"), vAST::UnOp::INVERT);}
}}
}},
{"binary",{
{"and","in0 & in1"},
{"or","in0 | in1"},
{"xor","in0 ^ in1"},
{"and",{"in0 & in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::AND, vAST::make_id("in1"));
}}},
{"or",{"in0 | in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::OR, vAST::make_id("in1"));
}}},
{"xor",{"in0 ^ in1",
[]() {return std::make_unique<vAST::BinaryOp>(vAST::make_id("in0"),
vAST::BinOp::XOR, vAST::make_id("in1"));
}}}
}},
{"other",{
{"mux","sel ? in1 : in0"},
{"concat","{in0, in1}"},
{"const","value"},
{"term",""},
{"tribuf","en ? in : 1'bz"},
{"ibuf","in"},
{"mux",{"sel ? in1 : in0",
[](){ return std::make_unique<vAST::TernaryOp>(
vAST::make_id("sel"),
vAST::make_id("in1"),
vAST::make_id("in0"));
}}},
{"concat",{"{in1,in0}",
[](){ return std::make_unique<vAST::Concat>(make_args({"in1", "in0"}));
}}},
{"const",{"value",
[](){ return vAST::make_id("value");
}}},
{"term",{"", [](){ return nullptr; }}},
{"tribuf",{"en ? in : 'hz",
[](){ return std::make_unique<vAST::TernaryOp>(
vAST::make_id("en"),
vAST::make_id("in"),
std::make_unique<vAST::NumericLiteral>("z", vAST::Radix::HEX));
}}},
{"ibuf",{"in",
[](){ return vAST::make_id("in");
}}}
}}
});

Expand Down Expand Up @@ -73,7 +105,7 @@ void CoreIRLoadVerilog_corebit(Context* c) {
for (auto it0 : bitVMap) {
for (auto it1 : it0.second) {
string op = it1.first;
string vbody = it1.second;
string vbody = it1.second.first;
json vjson;
vjson["prefix"] = "corebit_";
vjson["definition"] = " assign out = " + vbody + ";";
Expand All @@ -86,6 +118,8 @@ void CoreIRLoadVerilog_corebit(Context* c) {
ASSERT(bitIMap.count(it1.first),"missing" + it1.first);
vjson["interface"] = bitIMap.at(it1.first);
}
vjson["primitive_type"] = it0.first;
bit->getModule(op)->setPrimitiveExpressionLambda(it1.second.second);
bit->getModule(op)->getMetaData()["verilog"] = vjson;
}
}
Expand Down
3 changes: 2 additions & 1 deletion include/coreir/ir/generator.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4,10 +4,11 @@

#include "fwd_declare.h"
#include "globalvalue.h"
#include "coreir/primitive.h"

namespace CoreIR {

class Generator : public GlobalValue {
class Generator : public GlobalValue, public VerilogPrimitive {

TypeGen* typegen;

Expand Down
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