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feat: add spi1 to rock2 #374

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956b38a
feat: add spi1 to rock2
nascs Oct 24, 2024
812b0d1
Apply suggestions from code review
nascs Oct 25, 2024
01a912b
fix: fix the file name
nascs Oct 25, 2024
e56e737
fix: delete num-cs property
nascs Oct 25, 2024
bdd0106
feat: add enc28j60 common file
nascs Oct 25, 2024
b1cf9c3
feat: port enc28j60 to rk3528
nascs Oct 25, 2024
5bdb9b3
feat: add mcp2515 common file
nascs Oct 25, 2024
a3dfe7e
feat: port mcp2515 to rk3528
nascs Oct 25, 2024
fe6d841
fix: fix enc28j60 of rk3528
nascs Oct 25, 2024
5b993c2
feat: add w5500 common file
nascs Oct 25, 2024
d03187b
feat: port w5500 to rk3528
nascs Oct 25, 2024
1f5c26e
fix: fix spi compilation error
nascs Nov 1, 2024
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2 changes: 2 additions & 0 deletions arch/arm64/boot/dts/rockchip/overlays/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -136,9 +136,11 @@ dtb-$(CONFIG_CLK_RK3528) += \
rk3528-spi0-cs1-enc28j60.dtbo \
rk3528-spi0-cs1-mcp2515.dtbo \
rk3528-spi0-cs1-spidev.dtbo \
rk3528-spi0-cs1-w5500.dtbo \
rk3528-spi1-cs-gpio-enc28j60.dtbo \
rk3528-spi1-cs-gpio-mcp2515.dtbo \
rk3528-spi1-cs-gpio-spidev.dtbo \
rk3528-spi1-cs-gpio-w5500.dtbo \
rk3528-uart0-m0.dtbo \
rk3528-uart1-m0.dtbo \
rk3528-uart2-m1.dtbo \
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29 changes: 29 additions & 0 deletions arch/arm64/boot/dts/rockchip/overlays/rk3528-spi0-cs1-w5500.dts
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Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
#define W5500_SPI spi0
#define SPIDEV_NUM 1
#include "W5500.dtsi"

/ {
metadata {
title = "Enable W5500 on SPI0 CS1";
compatible = "radxa,rock-2a", "radxa,rock-2f", "radxa,medge-rk3528a-io";
category = "misc";
exclusive = "GPIO4_B2", "GPIO4_B3", "GPIO4_B4", "GPIO4_C1", "GPIO4_C6";
description = "Enable Microchip W5500 SPI Ethernet controller on SPI0 CS1.
INT=15";
};
};

&pinctrl {
w5500 {
w5500_int_pins: w5500-int-pins {
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

&eth_w5500 {
pinctrl-names = "default";
pinctrl-0 = <&W5500_int_pins>;
interrupt-parent = <&gpio4>;
interrupts = <RK_PC6 IRQ_TYPE_EDGE_FALLING>;
};
13 changes: 7 additions & 6 deletions arch/arm64/boot/dts/rockchip/overlays/rk3528-spi1-cs-gpio-enc28j60.dts
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
#define ENC28J60_SPI spi0
#define SPIDEV_NUM 1
#define ENC28J60_SPI spi1
#define SPIDEV_NUM 0
#include "enc28j60.dtsi"

/ {
Expand All @@ -13,10 +13,6 @@ INT=36";
};
};

#define ENC28J60_SPI spi0
#define SPIDEV_NUM 0
#include "enc28j60.dtsi"

&pinctrl {
enc28j60 {
enc28j60_int_pins: enc28j60-int-pins {
Expand All @@ -25,6 +21,11 @@ INT=36";
};
};

&ENC28J60_SPI {
cs-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&spi1_pins>;
};

&ethernet {
pinctrl-names = "default";
pinctrl-0 = <&enc28j60_int_pins>;
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34 changes: 34 additions & 0 deletions arch/arm64/boot/dts/rockchip/overlays/rk3528-spi1-cs-gpio-w5500.dts
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Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
#define W5500_SPI spi0
#define SPIDEV_NUM 1
#include "W5500.dtsi"

/ {
metadata {
title = "Enable W5500 on SPI1";
compatible = "radxa,rock-2a", "radxa,rock-2f", "radxa,medge-rk3528a-io";
category = "misc";
exclusive = "GPIO1_B4", "GPIO1_B6", "GPIO1_B7", "GPIO1_C0", "GPIO4_B6";
description = "Enable Microchip W5500 SPI Ethernet controller on SPI1.
INT=15";
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怎么其他的是36？

};
};

&pinctrl {
w5500 {
w5500_int_pins: w5500-int-pins {
rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

&W5500_SPI {
cs-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&spi1_pins>;
};

&eth_w5500 {
pinctrl-names = "default";
pinctrl-0 = <&w5500_int_pins>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PB4 IRQ_TYPE_EDGE_FALLING>;
};
26 changes: 26 additions & 0 deletions arch/arm64/boot/dts/rockchip/overlays/w5500.dtsi
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Original file line number Diff line number Diff line change
@@ -0,0 +1,26 @@
#ifndef __W5500_DTSI__
#define __W5500_DTSI__

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/interrupt-controller/irq.h>

/dts-v1/;
/plugin/;

#if !defined(W5500_SPI) && !defined(SPIDEV_NUM)
#error "Required macros are undefined: W5500_SPI and SPIDEV_NUM."
#endif

&W5500_SPI{
status = "okay";
#address-cells = <1>;
#size-cells = <0>;

eth_w5500: eth-w5500@0 {
status = "okay";
compatible = "wiznet,w5500";
reg = <0>;
spi-max-frequency = <30000000>;
};
};
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